US4484330A
Expired / Lapsed
US
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Majority vote circuit
Assignee: Nokia Bell Labs
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Filing: 1982-03-08
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Granted: 1984-11-20
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Expires: 2002-03-08
Abstract
Abstract A majority vote circuit determines when the majority of a group of signaling channels is properly conveying a common message in conjunction with a status signal individual to each channel. Respective status and message signals from each channel are scanned in pairs and in sequence. The number of valid message and status signals are accumulated in separate counters. A comparison circuit triggered by the completion of a scanning sequence matches counter outputs stage by stage to determine whether or not the count level in the message signal counter exceeds by one-half the count level in the status signal counter as an indication that a majority of a variable majority of the working channels conveys the same message signal.
Inventors
- 👤 Gar Moy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:41
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/187; H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
145 words
A majority vote circuit comprising a sole message source, a receiver for interpreting command messages from said source, a plurality of channels for transmitting command messages from said source to said receiver, a status signal generator at the terminus of each of said channels, first and second scanners for selecting in sequence command and status signals, respectively from said channels, first and second counters for accumulating the numbers of respective command and status signals in a scanning sequence by said first and second scanners, a register for storing the number of channels being scanned by said first and second scanners, and a comparator jointly responsive to the output counts in said first and second counters when said register number is reached for generating a majority vote signal indicating that the count stored in said first counter exceeds half the count stored in said second counter.
Claim 2
Dependent Claim
145 words
A majority vote circuit comprising a sole message source, a receiver for interpreting command messages from said source, a plurality of channels for transmitting command messages from said source to said receiver, a status signal generator at the terminus of each of said channels, first and second scanners for selecting in sequence command and status signals, respectively from said channels, first and second counters for accumulating the numbers of respective command and status signals in a scanning sequence by said first and second scanners, a register for storing the number of channels being scanned by said first and second scanners, and a comparator jointly responsive to the output counts in said first and second counters when said register number is reached for generating a majority vote signal indicating that the count stored in said first counter exceeds half the count stored in said second counter.
Claim 3
Dependent Claim
97 words
The majority vote circuit set forth in claim 1 in which said first and second scanners comprise a plurality of coincidence gates having an input for each transmitting channel and a plurality of further inputs for sequential enablement, a clock source, a multistage index counter responsive to said clock source, means for connecting the several stages of said counter to the further inputs of said coincidence gates according to a binary counting sequence to control the sequential enablement thereof, and a buffer gate for combining the output signals from said coincidence gates into a serial pulse train.
Claim 4
Dependent Claim
186 words
The majority vote circuit set forth in claim 1 in which said comparator comprises first means for matching each digit from said first counter with the digit of next lower significance from said second counter to determine whether the complete number stored in said first counter is greater or lesser than half the number stored in said second counter, second means for matching each digit from said first counter with the digit of next lower significance from said second counter to determine whether the digits from said first and second counters are equal, a first coincidence gate for each pair of digits being compared jointly responsive to said first and second matching means for producing a significant output when the corrected first matching means indicates that the digit from the first counter is greater than that from the second counter and outputs from all higher order second matching means indicate that the compared digits are equal, and an output coincidence gate for combining the outputs of said first coincidence gate to generate a majority-vote command signal when the output of any first coincidence gate is significant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-20 | 1988-05-21 | 1988-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-20 | 1992-05-21 | 1992-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-20 | 1996-05-21 | 1996-11-20 | $7700.00 | Window Closed / Lapsed |