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US4628512A
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US
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Address distribution in data storage apparatus
Assignee: OCHORIOS Ltd
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Filing: 1985-01-11
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Granted: 1986-12-09
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Expires: 2005-01-11
Abstract
Abstract In a data storage apparatus, memory chips are arranged in groups, each group having an address bus which is connected to the address inputs of all the chips in that group. Each address bus is terminated at both ends by circuits which perform the dual function of suppressing reflections and checking the addresses. Because reflections are suppressed, the time taken to address the store is reduced. One of the termination circuits in each group is arranged to compare the address on the bus with that on the bus in the adjacent group; the other circuit compares the address with a predetermined value.
Inventors
- 👤 Johnson Loo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763; G11; G11C; G11C8/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
138 words
Data storage apparatus comprising: (a) a plurality of groups of memory chips, each chip having an address input, (b) a plurality of address busses, one for each of said groups of memory chips, each address bus having a first end and a second end, and each address bus being connected in parallel to the address inputs of all the memory chips in the group in question, (c) means for applying an address signal in parallel to all the address busses, (d) first comparator means connected to the first end of each address bus, for comparing the address signal on that bus with the address signal on another one of the address busses, and (e) second comparator means connected to the second end of each address bus, for comparing the address signal on that bus with a predetermined value.
Claim 2
Dependent Claim
138 words
Data storage apparatus comprising: (a) a plurality of groups of memory chips, each chip having an address input, (b) a plurality of address busses, one for each of said groups of memory chips, each address bus having a first end and a second end, and each address bus being connected in parallel to the address inputs of all the memory chips in the group in question, (c) means for applying an address signal in parallel to all the address busses, (d) first comparator means connected to the first end of each address bus, for comparing the address signal on that bus with the address signal on another one of the address busses, and (e) second comparator means connected to the second end of each address bus, for comparing the address signal on that bus with a predetermined value.
Claim 3
Dependent Claim
27 words
Apparatus according to claim 1 further including logic means for combining outputs of said first and second comparator means to produce overall check signals for the apparatus.
Claim 4
Dependent Claim
73 words
Data storage apparatus according to claim 1 further including: (a) first and second address input paths, (b) a plurality of multiplexers each having first and second inputs connected respectively to the first and second address input paths, and each having an output, the multiplexers being operable in parallel to select the same address input path, and (c) means for connecting the output of each multiplexer to a respective plurality of said address busses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |