US4031523A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated storage system with parallel connection lines containing a resistor
Assignee: Digital Equipment Corp
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Filing: 1975-10-07
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Granted: 1977-06-21
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Expires: 1995-10-07
Abstract
Abstract A storage device, in particular a storage device composed of integrated circuits, comprising a number of multi-element stores and a drive unit which is connected to the multi-element stores via a number of parallel connection lines. The connection lines incorporate a series resistance device and a junction. Branch lines incorporating each time a series resistor as part of said series resistance device are connected between the junctions and groups of multi-element stores.
Inventors
- 👤 Johannes Bernardus Horsten
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:02
CPC Classifications
G; G11; G11C; G11C5/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
A memory system comprising a plurality of bit-organized storage cells, each cell storing a plurality of bits; a first network of first connecting lines connecting said storage cells, each one of said lines including a first junction point with at least another one of said lines, and a resistor connected in series with said one line; a plurality of drive units for supplying signals to said storage cells; and a second network of second connecting lines for connecting each of said drive units with at least one second junction point, said at least one second point being connected with said resistor of each respective one of said first connecting lines connected to said at least one second junction point a plurality of decoders, each one of said decoders being operatively associated with a respective one of said storage cells, a plurality of switches, each of said switches being in series with a respective one of said drive units, a clock pulse line associated with said storage cells, and a parasitic capacitance in each respective one of said decoders between each of said first connecting lines and said clock pulse line.
Claim 2
Dependent Claim
190 words
A memory system comprising a plurality of bit-organized storage cells, each cell storing a plurality of bits; a first network of first connecting lines connecting said storage cells, each one of said lines including a first junction point with at least another one of said lines, and a resistor connected in series with said one line; a plurality of drive units for supplying signals to said storage cells; and a second network of second connecting lines for connecting each of said drive units with at least one second junction point, said at least one second point being connected with said resistor of each respective one of said first connecting lines connected to said at least one second junction point a plurality of decoders, each one of said decoders being operatively associated with a respective one of said storage cells, a plurality of switches, each of said switches being in series with a respective one of said drive units, a clock pulse line associated with said storage cells, and a parasitic capacitance in each respective one of said decoders between each of said first connecting lines and said clock pulse line.
Claim 3
Dependent Claim
25 words
A memory system as defined in claim 1, wherein the number of resistors is fewer than the number of bit locations in the memory system.
Claim 4
Dependent Claim
18 words
A memory system as defined in claim 1, wherein said memory system is fabricated as an integrated circuit.
Claim 5
Dependent Claim
32 words
A memory system as defined in claim 1, where said drive unit comprises transistors, each of said transistors having an emitter; said second junction point being connected to one of said emitters.
Claim 6
Dependent Claim
44 words
A memory system as defined in claim 1, further comprising a plurality of capacitors connected between each respective one of said first connection line and ground; whereby said first network forms an integrating RC network with a minimal integration time per first connection line.
Claim 7
Dependent Claim
155 words
A memory system comprising a plurality of bit-organized storage cells, each cell storing a plurality of bits; a first network of first connecting lines connecting said storage cells, each one of said lines including a first junction point with at least another one of said lines, and a resistor connected in series with said one line; a plurality of drive units for supplying signals to said storage cells; and a second network of second connecting lines for connecting each of said drive units with at least one second junction point, said at least one second point being connected with said resistor of each respective one of said first connecting lines connected to said at least one second junction point; and a plurality of capacitors connected between each respective one of said first connection line and ground; whereby said first network forms an integrating RC network with a minimal integration time for each first connection line.
Claim 8
Dependent Claim
155 words
A memory system comprising a plurality of bit-organized storage cells, each cell storing a plurality of bits; a first network of first connecting lines connecting said storage cells, each one of said lines including a first junction point with at least another one of said lines, and a resistor connected in series with said one line; a plurality of drive units for supplying signals to said storage cells; and a second network of second connecting lines for connecting each of said drive units with at least one second junction point, said at least one second point being connected with said resistor of each respective one of said first connecting lines connected to said at least one second junction point; and a plurality of capacitors connected between each respective one of said first connection line and ground; whereby said first network forms an integrating RC network with a minimal integration time for each first connection line.
References Cited (Backward Citations)
US3360786A
Cited
US3727188A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-20 | 1980-12-20 | 1981-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-20 | 1984-12-20 | 1985-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-20 | 1988-12-20 | 1989-06-21 | $7700.00 | Window Closed / Lapsed |