Common memory control system with two bus masters

Claim 2

A data processing apparatus for controlling accessing of a memory comprising: memory means having a number of address locations; an address bus and a data bus; microprocessing means, operating in time with successively received clock signals and connected to said memory means via said data bus, for generating an address signal during a first period of at least one clock signal to specify one of said address locations in said memory means and for performing data transfer on said data bus between said microprocessing means and the address location in said memory means specified by said address signal during a second period of at least one clock signal following said first period; detection means for detecting said second period during which said data transfer is to be effected on said data bus between said microprocessing means and the specified address location in said memory means; bus master means separate from said microprocessing means for generating an address signal to specify an address location in said memory means for accessing said memory means; and bus control means connected to said microprocessing means, said bus master means and said address bus and responsive to the output of said detection means for supplying said address signal from said microprocessing means to said memory means only during said second period of data transfer between said microprocessing means and said memory means, and for supplying said address signal from said bus master means to said memory means to specify a different address location of said memory means whenever no data transfer is being effected between said microprocessing means and said memory means and at least during said first period.

Claim 3

A data processing apparatus comprising: memory means having a number of address locations; an address bus and a data bus; microprocessing means connected to memory means via said data bus for generating an address signal to specify one of said address locations in said memory means and for performing data transfer on said data bus between said microprocessing means and the address location in said memory means specified by said address signal; detection means for detecting the period during which said data transfer is to be effected on said data bus between said microprocessing means and the specified address location in said memory means; bus master means separate from said microprocessing means for generating an address signal to specify an address location in said memory means for accessing said memory means; and address bus control means connected to said microprocessing means and said address bus and responsive to the output of said detection means for supplying said address signal from said microprocessing means to said memory means only during said period of data transfer between said microprocessing means and said memory means, and for supplying said address signal from said bus master means to said memory means to specify a different address location of said memory means whenever no data transfer is being effected between said microprocessing means and said memory means, further comprising latching means for latching said address signal from said microprocessing means, said detection means including means for detecting the data transfer period from completion of latching of said address signal by said latching means until completion of a read/write control signal produced by said microprocessing means and said address bus control means including means for connecting said memory means to said latching means only during said data transfer period.

Claim 4

A data processing apparatus comprising: memory means having a number of address locations; an address bus and a data bus; microprocessing means connected to memory means via said data bus for generating an address signal to specify one of said address locations in said memory means and for performing data transfer on said data bus between said microprocessing means and the address location in said memory means specified by said address signal; detection means for detecting the period during which said data transfer is to be effected on said data bus between said microprocessing means and the specified address location in said memory means; bus master means separate from said microprocessing means for generating an address signal to specify an address location in said memory means for accessing said memory means; and address bus control means connected to said microprocessing means and said address bus and responsive to the output of said detection means for supplying said address signal from said microprocessing means to said memory means only during said period of data transfer between said microprocessing means and said memory means, and for supplying said address signal from said bus master means to said memory means to specify a different address location of said memory means whenever no data transfer is being effected between said microprocessing means and said memory means, further comprising latching means for latching said address signal from said microprocessing means, said detection means including means for detecting the data transfer period from completion of latching of said address signal by said latching means until completion of a read/write control signal produced by said microprocessing means and said address bus control means including means for connecting said memory means to said latching means only during said data transfer period.

Claim 5

A data processing apparatus according to claim 1, wherein said memory means comprises a dynamic memory which must be refreshed and said bus master means comprises a refresh counter which produces an address signal for refreshing said dynamic memory.

Claim 6

A data processing apparatus according to claim 1, wherein said bus master means comprises another microprocessing means which is independent from said microprocessing means.

Claim 7

A data processing apparatus according to claim 2, wherein said memory means comprises a dynamic memory which must be refreshed and said bus master means comprises a refresh counter which produces an address signal for refreshing said dynamic memory.

Claim 8

A data processing apparatus according to claim 2, wherein said bus master means comprises another microprocessing means which is independent from said microprocessing means.

Claim 9

A data processing apparatus, comprising: memory means having a number of address locations; an address bus and a data bus; microprocessing means connected to memory means via said data bus for generating an address signal to specify one of said address locations in said memory means and for performing data transfer on said data bus between said microprocessing means and the address location in said memory means specified by said address signal; detection means for detecting the period during which said data transfer is to be effected on said data bus between said microprocessing means and the specified address location in said memory means; bus master means separate from said microprocessing means for generating an address signal to specify an address location in said memory means for accessing said memory means; and address bus control means connected to said microprocessing means and said address bus and responsive to the output of said detection means for supplying said address signal from said microprocessing means to said memory means only during said period of data transfer between said microprocessing means and said memory means, and for supplying said address signal from said bus master means to said memory means to specify a different address location of said memory means whenever no data transfer is being effected between said microprocessing means and said memory means, wherein said microprocessing means includes means for producing a latching control signal during generation of said address signal by said microprocessing means and a read/write control signal for controlling reading and writing of data from and to said memory means, and further comprising a latch circuit connected to said microprocessing means for latching said address signal from said microprocessing means in response to said latching control signal.

Claim 10

A data processing apparatus, comprising: memory means having a number of address locations; an address bus and a data bus; microprocessing means connected to memory means via said data bus for generating an address signal to specify one of said address locations in said memory means and for performing data transfer on said data bus between said microprocessing means and the address location in said memory means specified by said address signal; detection means for detecting the period during which said data transfer is to be effected on said data bus between said microprocessing means and the specified address location in said memory means; bus master means separate from said microprocessing means for generating an address signal to specify an address location in said memory means for accessing said memory means; and address bus control means connected to said microprocessing means and said address bus and responsive to the output of said detection means for supplying said address signal from said microprocessing means to said memory means only during said period of data transfer between said microprocessing means and said memory means, and for supplying said address signal from said bus master means to said memory means to specify a different address location of said memory means whenever no data transfer is being effected between said microprocessing means and said memory means, wherein said microprocessing means includes means for producing a latching control signal during generation of said address signal by said microprocessing means and a read/write control signal for controlling reading and writing of data from and to said memory means, and further comprising a latch circuit connected to said microprocessing means for latching said address signal from said microprocessing means in response to said latching control signal.

Claim 11

A data processing apparatus according to claim 7, wherein said detection means includes means for detecting the data transfer period as a time which extends from the trailing edge of said latching control signal to the trailing edge of said read/write control signal.

Claim 12

A data processing apparatus according to claim 8, wherein said address bus control means comprises switching means connected to said latch circuit, said bus master means and said address bus, and which operates in response to the output of said detection means, for connecting said latch circuit to said address bus during said data transfer period and for connecting said bus master means to said address bus at all other times.

Claim 13

A data processing apparatus according to claim 9, wherein said memory means comprises a dynamic memory which must be refreshed and said bus master means comprises a refresh counter which produces an address signal for refreshing said dynamic memory.

Claim 14

A data processing apparatus according to claim 9, wherein said bus master means comprises another microprocessing means which is independent from said microprocessing means.