Patent US4627153A successfully refreshed from Google Patents.
US4627153A
Expired / Lapsed
US
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Method of producing a semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1985-04-15
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Granted: 1986-12-09
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Expires: 2005-04-15
Abstract
Abstract A static RAM using a flip-flop circuit as a memory cell is disclosed. The gate oxide film of the MOS transistor for selecting the memory cell is thicker than the gate oxide film of the MOS transistor included in the peripheral circuit of the memory matrix.
Inventors
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H10; H10B; H10B10/00; H10B10/12; H10B10/15; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
337 words
A method for manufacturing an MOS static RAM including enhancement type MOS transistors in a flip-flop circuit of a memory cell, enhancement type MOS transistors for selection of said memory cell, and enhancement type MOS transistors in a peripheral circuit, all said enhancement type transistors being formed in a common semiconductor substrate also containing a memory matrix, said method comprising the steps of: (a) forming a thick oxide film on a surface of said substrate; (b) removing portions of said thick oxide film from an area corresponding to an enhancement type MOS transistor formation region to expose a first area of said substrate surface; (c) forming a first gate oxide film on said exposed first area of said substrate surface; (d) forming a first polysilicon layer on said thick oxide film and on a portion of said first gate oxide film corresponding to said enhancement type MOS transistors for memory cell selection; (e) selectively removing said first polysilicon layer to form a gate electrode and a wiring layer for each enhancement type MOS transistor for memory cell selection; (f) removing said first gate oxide film from an area corresponding to said enhancement type MOS transistors in said peripheral circuit and in said flip-flop circuit to expose a second area of said substrate surface; (g) forming a second gate oxide film on said exposed second area of said substrate surface, said second gate oxide film being thinner than said first gate oxide film; (h) forming a second polysilicon layer on said thick oxide film and an area of said second gate oxide film corresponding to said enhancement type MOS transistors in said flip-flop circuit and in said peripheral circuit; (i) selectively removing said second polysilicon layer to provide a wiring layer and a gate electrode for each enhancement type MOS transistor in said flip-flop circuit and in said peripheral circuit; and (j) diffusing an impurity into source and drain formation regions of each of said enhancement type MOS transistors to form source and drain regions for said transistors.
Claim 2
Independent Claim
337 words
A method for manufacturing an MOS static RAM including enhancement type MOS transistors in a flip-flop circuit of a memory cell, enhancement type MOS transistors for selection of said memory cell, and enhancement type MOS transistors in a peripheral circuit, all said enhancement type transistors being formed in a common semiconductor substrate also containing a memory matrix, said method comprising the steps of: (a) forming a thick oxide film on a surface of said substrate; (b) removing portions of said thick oxide film from an area corresponding to an enhancement type MOS transistor formation region to expose a first area of said substrate surface; (c) forming a first gate oxide film on said exposed first area of said substrate surface; (d) forming a first polysilicon layer on said thick oxide film and on a portion of said first gate oxide film corresponding to said enhancement type MOS transistors for memory cell selection; (e) selectively removing said first polysilicon layer to form a gate electrode and a wiring layer for each enhancement type MOS transistor for memory cell selection; (f) removing said first gate oxide film from an area corresponding to said enhancement type MOS transistors in said peripheral circuit and in said flip-flop circuit to expose a second area of said substrate surface; (g) forming a second gate oxide film on said exposed second area of said substrate surface, said second gate oxide film being thinner than said first gate oxide film; (h) forming a second polysilicon layer on said thick oxide film and an area of said second gate oxide film corresponding to said enhancement type MOS transistors in said flip-flop circuit and in said peripheral circuit; (i) selectively removing said second polysilicon layer to provide a wiring layer and a gate electrode for each enhancement type MOS transistor in said flip-flop circuit and in said peripheral circuit; and (j) diffusing an impurity into source and drain formation regions of each of said enhancement type MOS transistors to form source and drain regions for said transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |