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US4625274A
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Microprocessor reset system
Assignee: Motorola Solutions Inc
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Filing: 1984-05-17
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Granted: 1986-11-25
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Expires: 2004-05-17
Abstract
Abstract A wireless telephone communication system 10 is provided in which a portable unit 12 communicates with a base unit 11 over a wireless (radio) communication link 15. Access to a telephone network 15b by the portable unit 12, via the base unit 11, is permitted when the base and portable units have corresponding ID codes stored therein. The base ID code is hardwired into the base unit 11, and the portable unit 12 learns its ID code from the base unit in response to mechanically coupling the base and portable units together via plug and socket assemblies 28 and 45. The base and portable units each have associated microprocessors 22 and 40 which implement the transfer of an ID code to the portable unit from the base unit via conductors (24'-42') which are part of the plug and socket assemblies. The plug and socket assemblies, when mated, also provide a connection between a battery charging supply circuit 25 in the base and a battery 46 in the portable. Reset circuits 29 and 50 are provided in the base and portable units and control the resetting of the microprocessors 22 and 40.
Inventors
- 👤 Daniel R. Schroeder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:53
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/72; H04M1/725; H04M1/727; G; G06; G06F; G06F1/00; G06F1/24
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
125 words
A microprocessor reset system comprising: a microprocessor having a reset input terminal, an information line coupled to said microprocessor on which said microprocessor will transmit information data, and reset means coupled between said information line and said microprocessor reset terminal for providing a reset pulse to said microprocessor in response to an initial predetermined signal transition on said information line which is preceded by the existence of a predetermined voltage level which exists for a predetermined minimum duration of time, said reset circuit effectively ignoring subsequent substantially identical signal transitions which occur on said information line during said transmission of information data unless they are directly preceded by the existence of said predetermined voltage level which exists for at least said minimum duration of time.
Claim 2
Dependent Claim
125 words
A microprocessor reset system comprising: a microprocessor having a reset input terminal, an information line coupled to said microprocessor on which said microprocessor will transmit information data, and reset means coupled between said information line and said microprocessor reset terminal for providing a reset pulse to said microprocessor in response to an initial predetermined signal transition on said information line which is preceded by the existence of a predetermined voltage level which exists for a predetermined minimum duration of time, said reset circuit effectively ignoring subsequent substantially identical signal transitions which occur on said information line during said transmission of information data unless they are directly preceded by the existence of said predetermined voltage level which exists for at least said minimum duration of time.
Claim 3
Dependent Claim
57 words
A microprocessor reset system according to claim 1 which includes a matable plug and socket assembly which when mated together provides a mechanical connection of said information line to a device external to said microprocessor, the mating of said plug and socket assembly also providing said initial predetermined signal transition which results in said microprocessor reset pulse.
Claim 4
Dependent Claim
107 words
A microprocessor reset system according to claim 2 wherein said reset means comprises a capacitor coupled between a first series terminal of a controllable series pass gate and said reset terminal, a first resistor means coupled from said reset terminal to a first predetermined reference voltage, a second resistor means coupled between said first series terminal and a reference voltage, and a control terminal of said gate coupled to said information line, said gate, when activated by a predetemined control voltage at its control terminal, providing at said reset terminal a second predetermined voltage different from said first predetermined reference voltage, said second voltage resetting said microprocessor.
Claim 5
Dependent Claim
42 words
A microprocessor reset system according to claim 3 wherein said series pass gate comprises a second series terminal coupled to a reference voltage different from said first reference voltage and wherein said second resistor means is coupled to said first reference voltage.
Claim 6
Dependent Claim
23 words
A microprocessor reset system according to claim 4 wherein said second resistor means has a magnitude substantially greater than said first resistor means.
Claim 7
Dependent Claim
50 words
A microprocessor reset system according to claim 1 which includes a matable connector means coupling said microprocessor to a device external to said microprocessor and also coupled to said information line for providing said initial signal transition in response to the mating of component parts of said matable connector means.
Claim 8
Dependent Claim
38 words
A microprocessor reset system according to claim 6 which includes circuitry in said reset means which provides said predetermined voltage level which precedes said signal transistion until the mating of the component parts of said matable connector means.
Claim 9
Dependent Claim
76 words
A microprocessor reset system according to claim 7 wherein said reset means includes a capacitor which responds to said predetermined pulse signal transitions to provide said reset pulse, and wherein said reset means includes a long time constant charging resistance means which together with said capacitor reenables said capacitor to produce said reset pulse in response to said pulse transitions if at least a minimum time duration elapses between the sequential occurrence of said pulse transitions.
Claim 10
Dependent Claim
39 words
A microprocessor reset system according to claim 6 wherein said reset circuit includes a short time constant charging resistance means which, in combination with said capacitor results in terminating said reset pulse prior to the transmission of said information.
Claim 11
Dependent Claim
59 words
A microprocessor reset system according to claim 1 wherein said transmitted information on said information line consists of substantially identical signal transitions to said initial signal transition but which are preceded by substantially similar predetermined voltage levels that exist for less than said minimum duration, whereby said microprocessor is not reset by said transmitted information generated by the microprocessor.
Claim 12
Dependent Claim
33 words
A microprocessor reset system according to claim 10 which includes a second microprocessor which receives said transmitted information on said information line and is reset in response to a portion of this information.
Claim 13
Dependent Claim
60 words
A microprocessor reset system according to claim 11 which includes a second reset means coupled between said information line and a reset terminal of said second microprocessor, said second reset circuit providing a reset pulse to said second microprocessor in response to the occurrence, on said information line, of a predetermined signal level for at least a minimum time duration.
Claim 14
Dependent Claim
28 words
A microprocessor reset system according to claim 12 wherein said second reset means includes a capacitor coupled in parallel with a resistor to said second microprocessor reset terminal.
Claim 15
Dependent Claim
30 words
A microprocessor reset system according to claim 13 wherein said second reset means includes a series pass gate coupled to between said information line and said second microprocessor reset terminal.
References Cited (Backward Citations)
US4486827A
Cited
US4328578A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-24 | 1990-05-26 | 1990-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-24 | 1994-05-26 | 1994-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-24 | 1998-05-26 | 1998-11-25 | $7700.00 | Window Closed / Lapsed |