Patent US4624739A successfully refreshed from Google Patents.
US4624739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process using dry etchant to avoid mask-and-etch cycle
Assignee: International Business Machines Corp
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Filing: 1985-08-09
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Granted: 1986-11-25
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Expires: 2005-08-09
Abstract
Abstract A process is disclosed for simultaneously etching holes in both the thick and thin portions of a dielectric layer on a semiconductor substrate. An anisotropic dry etchant is used to eliminate any significant lateral etching of the dielectric layer during etching. Thus, a mask-and-etch cycle may be eliminated from processing during integrated circuit manufacture, yet dimensional tolerances are maintained.
Inventors
- 👤 Paul E. Nixon
- 👤 Murty S. Polavarapu
- 👤 David Stanasolovich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:47
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; C; C03; C03C; C03C15/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
106 words
A process for simultaneously etching holes through both thick and thin portions of a layer on a substrate, comprising the steps of: masking the surface of said layer with a mask having a first window over said thin portion of said layer and a second window over said thick portion of said layer; exposing the upper surface of said layer through said first window and through said second window to an anisotropic dry etchant until said exposed layer in said first and said second windows is etched down to the substrate, said anisotropic dry etchant selectively etching said layer relative to said substrate and said mask.
Claim 2
Dependent Claim
106 words
A process for simultaneously etching holes through both thick and thin portions of a layer on a substrate, comprising the steps of: masking the surface of said layer with a mask having a first window over said thin portion of said layer and a second window over said thick portion of said layer; exposing the upper surface of said layer through said first window and through said second window to an anisotropic dry etchant until said exposed layer in said first and said second windows is etched down to the substrate, said anisotropic dry etchant selectively etching said layer relative to said substrate and said mask.
Claim 3
Dependent Claim
14 words
A process as described in claim 1, wherein said layer is a dielectric layer.
Claim 4
Dependent Claim
33 words
A process as described in claim 2, wherein said dielectric layer is a member of the group consisting of silicon dioxide, phosphosilicate glass, and a composite layer of silicon dioxide and phosphosilicate glass.
Claim 5
Dependent Claim
32 words
A process as described in claim 1, wherein said anisotropic dry etchant selectively etches said layer relative to said substrate and said mask at a ratio of at least 20 to 1.
Claim 6
Dependent Claim
32 words
A process as described in claim 2, wherein said anisotropic dry etchant selectively etches said layer relative to said substrate and said mask at a ratio of at least 20 to 1.
Claim 7
Dependent Claim
32 words
A process as described in claim 3, wherein said anisotropic dry etchant selectively etches said layer relative to said substrate and said mask at a ratio of at least 20 to 1.
Claim 8
Dependent Claim
20 words
A process as described in claim 1, wherein said anisotropic dry etchant is a gaseous mixture of hydrogen and carbontetrafluoride.
Claim 9
Dependent Claim
20 words
A process as described in claim 2, wherein said anisotropic dry etchant is a gaseous mixture of hydrogen and carbontetrafluoride.
Claim 10
Dependent Claim
20 words
A process as described in claim 3, wherein said anisotropic dry etchant is a gaseous mixture of hydrogen and carbontetrafluoride.
Claim 11
Dependent Claim
128 words
A process for simultaneously etching holes through both thick and thin portions of a dielectric layer on a semiconductor substrate, comprising the steps of: masking the surface of said dielectric layer with a mask having a first window over said thin portion of said dielectric layer and a second window over said thick portion of said dielectric layer; exposing the upper surface of said dielectric layer through said first window and through said second window to a gaseous mixture of hydrogen and carbon tetrafluoride until said exposed dielectric layer in said first and said second windows is etched down to the semiconductor substrate, said gaseous mixture selectively etching said dielectric layer relative to said semiconductor substrate and said mask at a ratio of at least 20 to 1.
Claim 12
Dependent Claim
128 words
A process for simultaneously etching holes through both thick and thin portions of a dielectric layer on a semiconductor substrate, comprising the steps of: masking the surface of said dielectric layer with a mask having a first window over said thin portion of said dielectric layer and a second window over said thick portion of said dielectric layer; exposing the upper surface of said dielectric layer through said first window and through said second window to a gaseous mixture of hydrogen and carbon tetrafluoride until said exposed dielectric layer in said first and said second windows is etched down to the semiconductor substrate, said gaseous mixture selectively etching said dielectric layer relative to said semiconductor substrate and said mask at a ratio of at least 20 to 1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-24 | 1990-05-26 | 1990-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-24 | 1994-05-26 | 1994-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-24 | 1998-05-26 | 1998-11-25 | $7700.00 | Window Closed / Lapsed |