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US4623962A
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US
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Register control processing system
Assignee: Fujitsu Ltd
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Filing: 1983-06-30
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Granted: 1986-11-18
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Expires: 2003-06-30
Abstract
Abstract This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated. The controls are thereby simplified in accordance with the kind of instruction to be performed. Namely, when an instruction is the LOAD instruction, the same content is loaded into both real an virtual registers from a respective address of the memory, and when it is the STORE instruction, the content from a respective virtual register is stored into the respective address of the memory.
Inventors
- 👤 Toshio Matsumoto
- 👤 Motokazu Kato
- 👤 Kiyosumi Sato
- 👤 Yoshihiro Mizushima
- 👤 Katsumi Ohnishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:12
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/30098; G06F9/30101; G06F9/3012; G06F9/30138; G06F9/30181; G06F9/30189; G06F9/34
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
87 words
A processing system comprising: at least one control register; a memory, respective addresses of which provide for a virtual register corresponding 1:1 to each said control register and for at least one further virtual register; means for respectively detecting a load control instruction and a store control instruction; and means for writing the same data into both the respective control register and the corresponding virtual register responsive to said load control instruction, and for reading only from the respective virtual register responsive to said store control instruction.
Claim 2
Dependent Claim
87 words
A processing system comprising: at least one control register; a memory, respective addresses of which provide for a virtual register corresponding 1:1 to each said control register and for at least one further virtual register; means for respectively detecting a load control instruction and a store control instruction; and means for writing the same data into both the respective control register and the corresponding virtual register responsive to said load control instruction, and for reading only from the respective virtual register responsive to said store control instruction.
Claim 3
Dependent Claim
108 words
A processing system comprising: a processor operated by instructions, said processor including a plurality of control registers of a number that is less than a maximum number of registers that can be designated by register designation data of said instructions of said processor; a memory for providing at respective addresses a plurality of virtual registers equal in number to or less than said maximum number; and means for executing processing for a first predetermined one of said instructions with respect to both the respective control register and the corresponding virtual register and for a second predetermined one of said instructions only with respect to the respective virtual register.
Claim 4
Dependent Claim
108 words
A processing system comprising: a processor operated by instructions, said processor including a plurality of control registers of a number that is less than a maximum number of registers that can be designated by register designation data of said instructions of said processor; a memory for providing at respective addresses a plurality of virtual registers equal in number to or less than said maximum number; and means for executing processing for a first predetermined one of said instructions with respect to both the respective control register and the corresponding virtual register and for a second predetermined one of said instructions only with respect to the respective virtual register.
Claim 5
Dependent Claim
20 words
The system of claim 2, wherein the number of said plurality of virtual registers is equal to said maximum number.
Claim 6
Dependent Claim
147 words
A data processing system comprising a plurality of control registers provided in hardware form, a memory, including a firmware part for storing at respective addresses instructions for performing a plurality of predetermined operations, and a virtual register part respective addresses of which serve as corresponding virtual registers, including a virtual register corresponding to each said control register and at least one further virtual register, means for determining when each said predetermined operation is to be performed and for referring to the respective instructions of said firmware part for performing the respective predetermined operation, wherein, for a first of said predetermined operations, the content of the same address of the memory is loaded into a respective control register and the corresponding virtual register, and, for a second of said predetermined operations, the content of only the respective virtual register is stored into a respective address of said memory.
Claim 7
Dependent Claim
147 words
A data processing system comprising a plurality of control registers provided in hardware form, a memory, including a firmware part for storing at respective addresses instructions for performing a plurality of predetermined operations, and a virtual register part respective addresses of which serve as corresponding virtual registers, including a virtual register corresponding to each said control register and at least one further virtual register, means for determining when each said predetermined operation is to be performed and for referring to the respective instructions of said firmware part for performing the respective predetermined operation, wherein, for a first of said predetermined operations, the content of the same address of the memory is loaded into a respective control register and the corresponding virtual register, and, for a second of said predetermined operations, the content of only the respective virtual register is stored into a respective address of said memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-17 | 1990-05-19 | 1990-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-17 | 1994-05-19 | 1994-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-17 | 1998-05-19 | 1998-11-18 | $7700.00 | Window Closed / Lapsed |