Combinational logic structure using PASS transistors

Claim 2

A logic circuit including as its basic element PASS transistors wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the transmission of signals from said input lead to said output lead, said logic circuit comprising: an output node; and a plurality of PASS transistors connected to receive a first input function, a second input function and a third input function supplied to said input leads and to receive a plurality of selected control signals applied to said control leads of said PASS transistors; where said first, second and third input functions are a reference voltage VSS, a supply voltage VDD and a carry variable C i+1 , said carry variable C i+1 input function being supplied to said input leads of two of said PASS transistors, said VSS and said VDD input functions being separately supplied to said input leads of two other of said PASS transistors, and said selected control signals are input variables to be added, A i , B i , said selected control signals, along with their complements A i and B i , being supplied to said control leads of said transistors, said input functions and said selected control signals being selectively combined in said PASS transistors, to produce a full adder carry out function at said output node.

Claim 3

A logic circuit in accordance with claim 1 in which the carry output therefrom, C i , is supplied in the form of C i+1 and C i+1 as input functions in the PASS logic circuitry to produce an output S i representing the sum of the full carry adder.

Claim 4

A logic circuit including as its basic element PASS transistors wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the transmission of signals from said input lead to said output lead, said logic circuit comprising: a pair of output nodes; and a plurality of PASS transistors connected to receive a plurality of input functions supplied to said input leads and to receive a plurality of selected control signals applied to said control leads of said plurality of PASS transistors; in which said input functions are a supply voltage VDD, a reference voltage VSS, input variables A, B, C and their complements A, B, C, said VSS input function being supplied as an input to said input leads of two of said PASS transistors, said VDD input function being supplied as an input to said input leads of two other of said PASS transistors, said B and said B functions being supplied separately to said input leads of two further of said PASS transistors, said input variables A, A, C, C being supplied to said control leads of said plurality of PASS transistors, said input functions and said selected control signals being selectively combined in said PASS transistors to produce a priority encoder logic circuit output function on said pair of output nodes; said priority encoder having two outputs D and E, said outputs D and E having the following relationship to said input variables A, B and C: ______________________________________ if A=1 DE=10 if A=0, B=1 DE=01 if A=0, B=0, C=1 DE=00 if A=0, B=0, C=0 DE=11 ______________________________________

Claim 5

A logic circuit including as its basic element PASS transistors wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the transmission of signals from said input lead to said output lead, said logic circuit comprising: a pair of output nodes; and a plurality of PASS transistors connected to receive a plurality of input functions supplied to said input leads and to receive a plurality of selected control signals applied to said control leads of said plurality of PASS transistors; in which said input functions are a supply voltage VDD, a reference voltage VSS, input variables A, B, C and their complements A, B, C, said VSS input function being supplied as an input to said input leads of two of said PASS transistors, said VDD input function being supplied as an input to said input leads of two other of said PASS transistors, said B and said B functions being supplied separately to said input leads of two further of said PASS transistors, said input variables A, A, C, C being supplied to said control leads of said plurality of PASS transistors, said input functions and said selected control signals being selectively combined in said PASS transistors to produce a priority encoder logic circuit output function on said pair of output nodes; said priority encoder having two outputs D and E, said outputs D and E having the following relationship to said input variables A, B and C: ______________________________________ if A=1 DE=10 if A=0, B=1 DE=01 if A=0, B=0, C=1 DE=00 if A=0, B=0, C=0 DE=11 ______________________________________

Claim 6

A logic circuit including as its basic element PASS transistors wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the transmission of signals from said input lead to said output lead, said logic circuit comprising: a pair of output nodes; and a plurality of PASS transistors connected to receive a plurality of first variable functions supplied to said input leads and to receive a plurality of selected control signals applied to said control leads of said PASS transistors, in which said input functions are T i-1 , T i-1 and a reference voltage VSS, and said control signals are Q i , Q i , D and D, said input functions and said selected control signals being selectively combined in said PASS transistors to produce a binary up/down counter logic device output at said pair of output nodes, said binary up/down counter having two outputs D i and T i , said outputs D i and T i having the following relationship to said input variables D, T i-1 Q i , ______________________________________ D T.sub.i-1 Q.sub.i D.sub.i T.sub.i ______________________________________ 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 1 0 1 1 0 1 1 0 1 1 ______________________________________

Claim 7

A logic circuit including as its basic element PASS transistors wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the transmission of signals from said input lead to said output lead, said logic circuit comprising: a pair of output nodes; and a plurality of PASS transistors connected to receive a plurality of first variable functions supplied to said input leads and to receive a plurality of selected control signals applied to said control leads of said PASS transistors, in which said input functions are T i-1 , T i-1 and a reference voltage VSS, and said control signals are Q i , Q i , D and D, said input functions and said selected control signals being selectively combined in said PASS transistors to produce a binary up/down counter logic device output at said pair of output nodes, said binary up/down counter having two outputs D i and T i , said outputs D i and T i having the following relationship to said input variables D, T i-1 Q i , ______________________________________ D T.sub.i-1 Q.sub.i D.sub.i T.sub.i ______________________________________ 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 1 0 1 1 0 1 1 0 1 1 ______________________________________

Claim 8

A logic circuit including as its basic element PASS transistors, wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the passing of signals from said input lead to said output lead, said logic circuit comprising: an output node; and at least two PASS transistors; means for supplying a first input function to said input lead of one of said transistors, said input function being Q i ; means for supplying a second input function to said input lead of another of said transistors, said second input function being Q i-1 ; and means for supplying selected control signals to said control leads of said transistors, said selected control signals being C, and C; said input function and said selected control signals being selectively combined in said PASS transistors to generate on said output mode a logic function D i representing a shift left/hold function; said output function D i having the following relationship to said variables C, Q i-1 , Q i ______________________________________ C Q.sub.i-1 Q.sub.i D.sub.i ______________________________________ 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 ______________________________________

Claim 9

A logic circuit including as its basic element PASS transistors, wherein each PASS transistor comprises an input lead, an output lead and a control lead for controlling the passing of signals from said input lead to said output lead, said logic circuit comprising: an output node; and at least two PASS transistors; means for supplying a first input function to said input lead of one of said transistors, said input function being Q i ; means for supplying a second input function to said input lead of another of said transistors, said second input function being Q i-1 ; and means for supplying selected control signals to said control leads of said transistors, said selected control signals being C, and C; said input function and said selected control signals being selectively combined in said PASS transistors to generate on said output mode a logic function D i representing a shift left/hold function; said output function D i having the following relationship to said variables C, Q i-1 , Q i ______________________________________ C Q.sub.i-1 Q.sub.i D.sub.i ______________________________________ 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 ______________________________________