Integrated circuit bipolar memory cell

Claim 2

A memory cell comprising: a semiconductor body including first and second bipolar transistors, each transistor including a base, a collector, and an emitter; the base of the first transistor being connected by a first connection to the collector of the second transistor and the collector of the first transistor being connected by a second connection to the base of the second transistor, the first and second connections including first and second spaced-apart strips of semiconductor material disposed on the semiconductor body; third and fourth spaced-apart strips of semiconductor material disposed across the first and second strips to contact the semiconductor body, but electrically isolated from the first and second strips; and first and second diode regions of semiconductor material disposed on selected portions of the respective first and second strips to contact the strips, the first and second diode regions being of opposite conductivity type to the selected portions of the first and second strips.

Claim 3

A memory cell as in claim 1 wherein the first and second strips of semiconductor material comprise polycrystalline silicon.

Claim 4

A memory cell as in claim 2 wherein the selected portions of the first and second strips are doped with N conductivity type impurity and the first and second diode regions of semiconductor material are doped with P conductivity type impurity.

Claim 5

A memory cell as in claim 2 wherein at least part of each of the first and second strips other than the selected portions is doped with P conductivity type impurity.

Claim 6

A memory cell as in claim 4 wherein each of the first and second strips includes a PN junction.

Claim 7

A memory cell as in claim 5 wherein each of the first and second strips further comprises a region of a metal silicide disposed across the PN junction to short circuit the PN junction.

Claim 8

A memory cell as in claim 6 wherein the metal silicide comprises a refractory metal silicide.

Claim 9

A memory cell as in claim 1 wherein each of the third and fourth spaced-apart strips of semiconductor material comprises polycrystalline silicon.

Claim 10

A memory cell as in claim 8 wherein each of the third and fourth spaced-apart strips are doped with P conductivity type impurity.

Claim 11

A memory cell as in claim 1 wherein the emitters of each of the first and second bipolar transistors comprise a buried layer in the semiconductor body.

Claim 12

A memory cell as in claim 10 wherein the semiconductor body further comprises an epitaxial layer disposed across the buried layer and divided into at least first and second pockets electrically isolated from each other by a region of oxidized semiconductor material extending into the semiconductor body to the buried layer.

Claim 13

A memory cell as in claim 11 wherein a portion of the epitaxial layer in the first pocket comprises the base of the first transistor, and a portion of the epitaxial layer in the second pocket comprises a base of the second transistor.

Claim 14

A memory cell as in claim 12 wherein the collector of the first transistor comprises a doped region extending into the epitaxial layer in the first pocket, and the collector of the second transistor comprises a doped region extending into the epitaxial layer in the second pocket.

Claim 15

An integrated bipolar memory cell including first and second cross-coupled transistors comprising: a semiconductor substrate of first conductivity type, the substrate having a first surface; a buried layer region of second conductivity type in the substrate adjacent the first surface, the buried layer providing commonly connected emitters for the first and second transistors; a first and a second pocket of first conductivity type epitaxial semiconductor material disposed on at least the buried layer region, each pocket surrounded by insulating material, first portions of each of the first and second pockets adjacent the buried layer providing bases for the first and second transistors, respectively, and second portions of each of the first and second pockets providing base contacts to the respective bases; first and second collector regions of second conductivity type disposed on the corresponding first portions of the respective pockets to thereby provide collectors for the first and second transistors, respectively; first and second spaced-apart connections of semiconductor material disposed on at least the epitaxial semiconductor material, the first connection extending from the collector of the first transistor to the base contact of the second transistor, the second connection extending from the collector of the second transistor to the base contact of the first transistor, separate portions of each of the connections being of conductivity type corresponding to the conductivity type of the collector or base contact beneath that portion of the connection; first and second shorting regions of electrically conductive material disposed on the corresponding connections to thereby electrically short the collector of the first transistor to the base contact of the second transistor, and the collector of the second transistor to the base contact of the first transistor; first and second spaced-apart strips of first conductivity type semiconductor material disposed on at least the second portion of the respective first and second pockets; and first and second diode regions of first conductivity type semiconductor material disposed on the separate portions of the respective first and second connections, the separate portions being of conductivity type corresponding to the collectors of the respective first and second transistors.

Claim 16

An integrated bipolar memory cell including first and second cross-coupled transistors comprising: a semiconductor substrate of first conductivity type, the substrate having a first surface; a buried layer region of second conductivity type in the substrate adjacent the first surface, the buried layer providing commonly connected emitters for the first and second transistors; a first and a second pocket of first conductivity type epitaxial semiconductor material disposed on at least the buried layer region, each pocket surrounded by insulating material, first portions of each of the first and second pockets adjacent the buried layer providing bases for the first and second transistors, respectively, and second portions of each of the first and second pockets providing base contacts to the respective bases; first and second collector regions of second conductivity type disposed on the corresponding first portions of the respective pockets to thereby provide collectors for the first and second transistors, respectively; first and second spaced-apart connections of semiconductor material disposed on at least the epitaxial semiconductor material, the first connection extending from the collector of the first transistor to the base contact of the second transistor, the second connection extending from the collector of the second transistor to the base contact of the first transistor, separate portions of each of the connections being of conductivity type corresponding to the conductivity type of the collector or base contact beneath that portion of the connection; first and second shorting regions of electrically conductive material disposed on the corresponding connections to thereby electrically short the collector of the first transistor to the base contact of the second transistor, and the collector of the second transistor to the base contact of the first transistor; first and second spaced-apart strips of first conductivity type semiconductor material disposed on at least the second portion of the respective first and second pockets; and first and second diode regions of first conductivity type semiconductor material disposed on the separate portions of the respective first and second connections, the separate portions being of conductivity type corresponding to the collectors of the respective first and second transistors.