US4412239A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polysilicon interconnects with pin poly diodes
Assignee: Toshiba Corp
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Filing: 1980-04-07
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Granted: 1983-10-25
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Expires: 2000-04-07
Abstract
Abstract A semiconductor device comprising a semiconductor substrate, a plurality of IIL gates formed in the substrate, each consisting of an inverter transistor and an injector transistor, and polysilicon films of P and N conductivity types connected to each other and formed as electrode layers connected with diffusion layers of P and N conductivity types which are formed on the substrate, respectively.
Inventors
- 👤 Hiroshi Iwasaki
- 👤 Osamu Ozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D62/00; H10D62/40; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
102 words
A semiconductor device comprising: a semiconductor substrate; an integrated circuit having a plurality of bipolar transistors formed in the substrate, each transistor including a diffusion layer of P conductivity type and a diffusion layer of N conductivity type; a polysilicon film of P conductive type formed as an electrode on the diffusion layer of P conductivity type of each transistor: a polysilicon film of N conductivity type formed as an electrode on the diffusion layer of N conductivity type of each transistor; a P-N junction formed between the P and N polysilicon films; and a PIN diode formed at the P-N junction.
Claim 2
Dependent Claim
102 words
A semiconductor device comprising: a semiconductor substrate; an integrated circuit having a plurality of bipolar transistors formed in the substrate, each transistor including a diffusion layer of P conductivity type and a diffusion layer of N conductivity type; a polysilicon film of P conductive type formed as an electrode on the diffusion layer of P conductivity type of each transistor: a polysilicon film of N conductivity type formed as an electrode on the diffusion layer of N conductivity type of each transistor; a P-N junction formed between the P and N polysilicon films; and a PIN diode formed at the P-N junction.
Claim 3
Dependent Claim
81 words
A semiconductor device according to claim 1, wherein said bipolar transistors constitute integrated injection logic gates, each gate comprising a vertical bipolar transistor inverter of a first conductivity type and a lateral bipolar transistor injector of a second conductivity type, an emitter region of the vertical transistor and a base region of the lateral transistor comprising a first common region and a base region of the vertical transistor and a collector region of the lateral transistor comprising a second common region.
Claim 4
Dependent Claim
102 words
A semiconductor device comprising: a semiconductor substrate; an integrated circuit having a plurality of bipolar transistors formed in the substrate, each transistor including a diffusion layer of P conductivity type and a diffusion layer of N conductivity type; a polysilicon film of P conductivity type formed as an electrode on the diffusion layer of P conductivity type of each transistor; a polysilicon film of N conductivity type formed as an electrode on the diffusion layer of N conductivity type of each transistor; and an amorphous portion provided between the P and N polysilicon films and connecting the P and N polysilicon films.
Claim 5
Dependent Claim
102 words
A semiconductor device comprising: a semiconductor substrate; an integrated circuit having a plurality of bipolar transistors formed in the substrate, each transistor including a diffusion layer of P conductivity type and a diffusion layer of N conductivity type; a polysilicon film of P conductivity type formed as an electrode on the diffusion layer of P conductivity type of each transistor; a polysilicon film of N conductivity type formed as an electrode on the diffusion layer of N conductivity type of each transistor; and an amorphous portion provided between the P and N polysilicon films and connecting the P and N polysilicon films.
Claim 6
Dependent Claim
81 words
A semiconductor device according to claim 3, wherein said bipolar transistors constitute integrated injection logic gates, each gate comprising a vertical bipolar transistor inverter of a first conductivity type and a lateral bipolar transistor injector of a second conductivity type, an emitter region of the vertical transistor and a base region of the lateral transistor comprising a first common region and a base region of the vertical transistor and a collector region of the lateral transistor comprising a second common region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-24 | 1987-04-25 | 1987-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-24 | 1991-04-25 | 1991-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-24 | 1995-04-25 | 1995-10-25 | $7700.00 | Window Closed / Lapsed |