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US4622512A
Expired / Lapsed
US
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Band-gap reference circuit for use with CMOS IC chips
Assignee: Analog Devices Inc
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Filing: 1985-02-11
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Granted: 1986-11-11
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Expires: 2005-02-11
Abstract
Abstract A band-gap reference circuit having a pair of transistors operated at different current densities to produce a positive temperature coefficient (TC) signal proportional to the ΔV BE of the two transistors and combined with a negative TC voltage derived from the V BE of one of the transistors to produce a composite signal substantially invariant with temperature. The ΔV BE signal component is increased in magnitude by connecting resistor string bias circuit to each of the transistors, to effectively multiply the V BE of each transistor, and thereby multiply the ΔV BE signal. The composite signal is sensed in the emitter circuits of the two transistors, so that it is unnecessary to access the collectors of the transistors, thereby making it readily possible to use the circuit with CMOS IC devices.
Inventors
- 👤 Adrian P. Brokaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:09
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
67 words
A band-gap reference circuit comprising: first and second transistors operable at different current densities to produce a ΔV BE signal as a function of temperature; first and second V BE multiplier circuits each connected to the base and emitter of a corresponding one of said transistors; and output terminal means coupled to said transistors to develop a ΔV BE signal multiplied in magnitude by said multiplier circuits.
Claim 2
Dependent Claim
67 words
A band-gap reference circuit comprising: first and second transistors operable at different current densities to produce a ΔV BE signal as a function of temperature; first and second V BE multiplier circuits each connected to the base and emitter of a corresponding one of said transistors; and output terminal means coupled to said transistors to develop a ΔV BE signal multiplied in magnitude by said multiplier circuits.
Claim 3
Dependent Claim
32 words
A circuit as in claim 1, wherein each of said multiplier circuits comprises at least two series-connected resistors one of which is connected between the base and emitter of the corresponding transistor.
Claim 4
Dependent Claim
52 words
A circuit as in claim 2, including first and second resistor means connected between common and the emitter of a respective transistor; one of said resistor means comprising at least two resistors forming a voltage divider to establish at the junction of said two resistors one terminal of said output terminal means.
Claim 5
Dependent Claim
43 words
A circuit as in claim 1, wherein each of said multiplier circuits includes first resistive means connected between the base of the corresponding transistor and a reference voltage, and second resistive means connected between the base and the emitter of the corresponding transistor.
Claim 6
Dependent Claim
26 words
A circuit as in claim 4, including first and second emitter resistor means each connected between a common line and the emitter of a corresponding transistor.
Claim 7
Dependent Claim
53 words
A circuit as in claim 5, wherein one of said emitter resistor means comprises at least two series-connected resistors forming a voltage divider; said output terminal means having one terminal at the junction between two of said series-connected resistors; said output terminal means having a second terminal connected to the emitter resistor means.
Claim 8
Dependent Claim
62 words
A circuit as in claim 1, wherein said multiplier circuits are connected to a voltage reference line to produce current therethrough; an amplifier having its input connected to said output terminal means to receive the signal therefrom; and means connecting the output of said amplifier to said voltage reference line in a negative feedback sense to stabilize the voltage of said line.
Claim 9
Dependent Claim
67 words
A circuit as in claim 7, wherein each of said multiplier circuits comprises a resistor string; one end of each string being connected to said voltage reference line; the other end of each string being connected to the emitter of a respective one of said transistors; the base of each of said transistors being connected to an intermediate junction of a corresponding one of said resistor strings.
Claim 10
Dependent Claim
55 words
A circuit as in claim 8, including two series resistors connected between common and the emitter of one of said transistors; at least one resistor connected between common and the emitter of the other transistor; said amplifier input being connected between the emitter of said other transistor and the junction of said two series resistors.
Claim 11
Dependent Claim
26 words
A circuit as in claim 7, wherein the collectors of said transistors are connected to voltages which are different from the voltage of said reference line.
References Cited (Backward Citations)
US4263519A
Cited
US4317054A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-10 | 1990-05-12 | 1990-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-10 | 1994-05-12 | 1994-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-10 | 1998-05-12 | 1998-11-11 | $7700.00 | Window Closed / Lapsed |