Logic circuit with MOSFETs arranged to reduce current flow

Claim 2

A logic circuit for producing an output signal responsive to input signals comprising: first and second power source terminals; and output terminal; a plurality of MOSFETs of a first conductivity type having current conducting terminals connected in parallel between said first power source terminal and said output terminal, each of said MOSFETs being controlled by one of said input signals, respectively, and only one MOSFET of a second conductivity type having current conducting terminals connected between said second power source terminal and output terminal and controlled by one of said input signals which necessarily controls one of said plurality of MOSFETs, the channel resistance of said MOSFET of second conductivity type when conducting being larger than that of each one of said MOSFETs of first conductivity type when conducting.

Claim 3

A logic circuit according to claim 1 wherein said MOSFETs of first conductivity type are N-channel MOSFETs and said MOSFET of second conductivity type is a P-channel MOSFET.

Claim 4

A logic circuit according to claim 2 wherein said N-channel MOSFETs and P-channel MOSFET are enhancement type.

Claim 5

A logic circuit according to claim 3 wherein the voltage applied to said first power source terminal is lower than the voltage applied to said second power source terminal.

Claim 6

A logic circuit according to claim 2 wherein said N-channel MOSFETs are enhancement type and said P-channel MOSFET is depletion type.

Claim 7

A logic circuit according to claim 5 wherein the voltage applied to said first power source terminal is lower than the voltage applied to said second power source terminal.

Claim 8

A logic circuit according to claim 1 wherein said MOSFETs of first conductivity type are P-channel MOSFETs and said MOSFET of second conductivity type is a N-channel MOSFET.

Claim 9

A logic circuit according to claim 7 wherein said P-channel MOSFETs and N-channel MOSFET are enhancement type.

Claim 10

A logic circuit according to claim 8 wherein the voltage applied to said first power source terminal is higher than the voltage applied to said second power source terminal.

Claim 11

A logic circuit according to claim 7 wherein said P-channel MOSFETs are enhancement type and said N-channel MOSFET is depletion type.

Claim 12

A logic circuit according to claim 10 wherein the voltage applied to said first power source terminal is higher than the voltage applied to said second power source terminal.

Claim 13

A logic circuit according to claim 1 further comprising means for generating said input signals, said generating means applying to said MOSFET of second conductivity type, one of said input signals which has a binary level for a greater percentage of time than any other of said input signals, said level causing said MOSFET of second conductivity type to be nonconductive.

Claim 14

A logic circuit for producing an output signal responsive to input signals comprising: first and second power source terminals; an output terminal; a plurality of MOSFETs of first conductivity type having current conducting terminals connected in parallel between said first power source terminal and output terminal, each of said MOSFETs being controlled by one of said input signals, respectively, and a plurality of MOSFETs of second conductivity type having current conducting terminals connected in series between said second power source terminal and output terminal, each of said MOSFETs of second conductivity type being controlled by one of said input signals which necessarily controls one of said plurality of MOSFETs of first conductivity type, respectively, the number of MOSFETs of second conductivity type being less than that of said MOSFETs of first conductivity type, the total resistance of the channel resistance of said MOSFETs of second conductivity type when conducting is larger than that of each one of said MOSFETs of first conductivity type when conducting.

Claim 15

A logic circuit for producing an output signal responsive to input signals comprising: first and second power source terminals; an output terminal; a plurality of MOSFETs of first conductivity type having current conducting terminals connected in parallel between said first power source terminal and output terminal, each of said MOSFETs being controlled by one of said input signals, respectively, and a plurality of MOSFETs of second conductivity type having current conducting terminals connected in series between said second power source terminal and output terminal, each of said MOSFETs of second conductivity type being controlled by one of said input signals which necessarily controls one of said plurality of MOSFETs of first conductivity type, respectively, the number of MOSFETs of second conductivity type being less than that of said MOSFETs of first conductivity type, the total resistance of the channel resistance of said MOSFETs of second conductivity type when conducting is larger than that of each one of said MOSFETs of first conductivity type when conducting.

Claim 16

A logic circuit according to claim 13 wherein said MOSFETs of first conductivity type are N-channel MOSFETs and said MOSFETs of second conductivity type are P-channel MOSFETs.

Claim 17

A logic circuit according to claim 14 wherein said N-channel MOSFETs and P-channel MOSFETS are enhancement type.

Claim 18

A logic circuit according to claim 15 wherein the voltage applied to said first power source terminal is lower than the voltage applied to said second power source terminal.

Claim 19

A logic circuit according to claim 14 wherein said N-channel MOSFETs are enhancement type and said P-channel MOSFETS are depletion type.

Claim 20

A logic circuit according to claim 17 wherein the voltage applied to said first power source terminal is lower than the voltage applied to said second power source terminal.

Claim 21

A logic circuit according to claim 13 wherein said MOSFETs of first conductivity type are P-channel MOSFETs and said MOSFETs of second conductivity type are N-channel MOSFET.

Claim 22

A logic circuit according to claim 19 wherein said P-channel MOSFETs and N-channel MOSFETs are enhancement type.

Claim 23

A logic circuit according to claim 20 wherein the voltage applied to said first power source terminal is higher than the voltage applied to said second power source terminal.

Claim 24

A logic circuit according to claim 19 wherein said P-channel MOSFETs are enhancement type and said N-channel MOSFETs are depletion type.

Claim 25

A logic circuit according to claim 22 wherein the voltage applied to said first power source terminal is higher than the voltage applied to said second power source terminal.

Claim 26

A logic circuit according to claim 13 further comprising means for generating said nput signals, said generating means applying to said MOSFETs of second conductivity type those input signals which cause at least one of said MOSFETs of second conductivity type to be nonconductive for the greatest percentage of time.

Claim 27

A logic circuit for producing an output signal responsive to binary input signals comprising: means for generating said input signals, one of said input signals having a binary level for a greater percentage of time than any of the other said input signals; first and second power source terminals; an output terminal; a plurality of MOSFETs of a first conductivity type having current conducting terminals connected in parallel between said first power source terminal and said output terminal, each of said MOSFETs being controlled by one of said input signals including said one input signal, respectively, to be conductive in response to said binary level; and at least one MOSFET of a second conductivity type having current conducting terminals connected between said second power source terminal and output terminal, one of said at least one MOSFET being controlled by said one input signal to be nonconductive in response to said binary level, any other of said at least one MOSFET each being controlled by a different one of said input signals which necessarily control any of said plurality of MOSFETs, respectively, the number of said at least one MOSFET being less than that of said MOSFETs of said first conductivity type, the channel resistance of said at least one MOSFET when conducting being larger than that of each one of said plurality of MOSFETs when conducting.

Claim 28

A logic circuit for producing an output signal responsive to binary input signals comprising: means for generating said input signals, one of said input signals having a binary level for a greater percentage of time than any of the other said input signals; first and second power source terminals; an output terminal; a plurality of MOSFETs of a first conductivity type having current conducting terminals connected in parallel between said first power source terminal and said output terminal, each of said MOSFETs being controlled by one of said input signals including said one input signal, respectively, to be conductive in response to said binary level; and at least one MOSFET of a second conductivity type having current conducting terminals connected between said second power source terminal and output terminal, one of said at least one MOSFET being controlled by said one input signal to be nonconductive in response to said binary level, any other of said at least one MOSFET each being controlled by a different one of said input signals which necessarily control any of said plurality of MOSFETs, respectively, the number of said at least one MOSFET being less than that of said MOSFETs of said first conductivity type, the channel resistance of said at least one MOSFET when conducting being larger than that of each one of said plurality of MOSFETs when conducting.

Claim 29

A logic circuit as in claim 25 wherein said at least one MOSFET consists of only one MOSFET.