Integrated circuit packaging systems with double surface heat dissipation

Claim 2

A mounting arrangement for a semiconductor chip having a bottom surface and a top surface with an integrated circuit fashioned thereon, including a plurality of bonding pads disposed around the periphery of said top surface, comprising: (a) a first heat sink having a mounting surface corresponding substantially to the area of said bottom surface of said chip; (b) first means for mounting said mounting surface of said first heat sink to said bottom surface of said chip in good heat transfer relation; (c) a second heat sink having a mounting surface corresponding substantially to a region of said top surface of said chip interior to said bonding pads; (d) second means for mounting said second heat sink to said top surface of said chip in good heat transfer relation wherein said top surface of said chip has a passivation layer of electrical insulating material deposited thereon and a layer of gold formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said second heat sink and wherein said second mounting means includes a solder preform formed of a low temperature alloy for bonding said second heat sink to said mounting pad.

Claim 3

The integrated circuit chip mounting arrangement of claim 1, wherein between said layer of gold and said passivation layer are formed an adhesion metal layer on said passivation layer and a diffusion barrier metal layer on said adhesion metal layer, wherein said gold layer is formed on said diffusion barrier metal layer said adhesion and diffusion layers including, respectively, chrome and copper, titanium and palladium, titanium and platinum or platinum and tungsten.

Claim 4

The integrated circuit chip mounting arrangement of claim 1, wherein said mounting surface of said first heat sink has a layer of gold formed thereon and said first mounting means comprises one of a gold-silicon preform for forming a gold-silicon eutectic bond between said heat sink and said chip or a layer of gold-chromium alloy formed on said bottom surface of said chip together with a solder preform formed of a low temperature alloy for bonding said gold layer on said first heat sink to said gold-chromium alloy layer on said chip.

Claim 5

The mounting arrangement of any of claims 1, 2 or 3, further comprising: (a) a substrate having a bonding pad and circuit lead arrangement formed on a substantially planar top surface thereof; means for mounting said semiconductor chip on said top surface of said substrate in an inverted orientation, said top surface of said chip being separated from said top surface of said substrate by a prearranged separation distance, said top surface of said substrate having a heat sink mounting pad thereon, said second heat sink having a thickness substantially corresponding to said separation distance; and (b) third means for mounting said second heat sink to said heat sink mounting pad in good heat transfer relation.

Claim 6

The mounting arrangement of claim 4, wherein said top surface of said heat sink bonding pad is a layer of gold and said third mounting means comprises a solder perform formed of a low temperature alloy for bonding said second heat sink to said gold layer on said heat sink bonding pad.

Claim 7

The mounting arrangement of claim 4, further comprising encapsulating means formed on said substrate over at least a portion of said chip, said first heat sink including a first heat sink body having a cross-sectional area substantially corresponding to said bottom surface of said semiconductor chip and a second heat sink body having a larger cross-sectional area mounted to said first heat sink body.

Claim 8

The mounting arrangement of any of claims 1, 2 or 3 wherein said first heat sink comprises a substrate having a bonding pad and circuit lead arrangement formed on the top surface thereof and a chip mounting pad formed on said top surface to define said first heat sink mounting surface.

Claim 9

The mounting arrangement of claim 7, further comprising encapsulating means formed on said substrate over said chip and a lower portion of said second heat sink, said second heat sink including a first heat sink body having a cross-sectional area substantially corresponding to the associated area of said semiconductor ship to which it is bonded and a second heat sink body having a larger cross-sectional area mounted to said first heat sink body.

Claim 10

A mounting arrangement for a semiconductor chip having a bottom surface and a top surface with an integrated circuit fashioned thereon, including a plurality of bonding pads disposed around the periphery of said top surface comprising: (a) a printed circuit substrate having a substantially planar top surface with a bonding pad and circuit lead arrangement formed thereon; (b) means for mounting said semiconductor chip on said substrate in an inverted orientation with said top surface of said chip separated from the top surface of said substrate and including means for electrically connecting said chip bonding pads to said bonding pad and circuit lead arrangement of said substrate; (c) a first heat sink mounted to said bottom surface of said chip; and (d) a second heat sink having a first surface mounted to a portion of said top surface of said chip interior to said bonding pads and a second surface mounted to said top surface of said substrate, wherein said top surface of said chip has a passivation layer of electrical insulating material deposited thereon and a layer formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said second heat sink and wherein said second mounting means includes a low temperature alloy for bonding said second heat sink to said mounting pad.

Claim 11

A mounting arrangement for a semiconductor chip having a bottom surface and a top surface with an integrated circuit fashioned thereon, including a plurality of bonding pads disposed around the periphery of said top surface comprising: (a) a printed circuit substrate having a substantially planar top surface with a bonding pad and circuit lead arrangement formed thereon; (b) means for mounting said semiconductor chip on said substrate in an inverted orientation with said top surface of said chip separated from the top surface of said substrate and including means for electrically connecting said chip bonding pads to said bonding pad and circuit lead arrangement of said substrate; (c) a first heat sink mounted to said bottom surface of said chip; and (d) a second heat sink having a first surface mounted to a portion of said top surface of said chip interior to said bonding pads and a second surface mounted to said top surface of said substrate, wherein said top surface of said chip has a passivation layer of electrical insulating material deposited thereon and a layer formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said second heat sink and wherein said second mounting means includes a low temperature alloy for bonding said second heat sink to said mounting pad.

Claim 12

A mounting arrangement for a semiconductor chip having a bottom surface and a top surface with an integrated circuit fashioned thereon comprising: (a) a printed circuit substrate having a top surface with a chip mounting pad and a bonding pad and circuit arrangement formed thereon; (b) means for mounting said bottom surface of said semiconductor chip to said chip mounting pad in good heat transfer relation; (c) means for connecting said bonding pads on said chip to said bonding pad and circuit lead arrangement on said substrate; (d) a heat sink having a bottom mounting area substantially corresponding to an area of said top surface of said chip interior to said bonding pad; and (e) means for mounting said heat sink to said top surface area of said chip in good heat transfer relation, wherein said top surface of said chip has a passivation layer of electrical insulating material deposited thereon and a layer formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said heat sink.

Claim 13

A mounting arrangement for a semiconductor chip having a bottom surface and a top surface with an integrated circuit fashioned thereon comprising: (a) a printed circuit substrate having a top surface with a chip mounting pad and a bonding pad and circuit arrangement formed thereon; (b) means for mounting said bottom surface of said semiconductor chip to said chip mounting pad in good heat transfer relation; (c) means for connecting said bonding pads on said chip to said bonding pad and circuit lead arrangement on said substrate; (d) a heat sink having a bottom mounting area substantially corresponding to an area of said top surface of said chip interior to said bonding pad; and (e) means for mounting said heat sink to said top surface area of said chip in good heat transfer relation, wherein said top surface of said chip has a passivation layer of electrical insulating material deposited thereon and a layer formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said heat sink.

Claim 14

The mounting arrangement of either claim 9 or 10, further comprising encapsulating means formed on said substrate over said chip, said outer heat sink including a first heat sink body having a cross-sectional area substantially corresponding to the associated area of said semiconductor chip to which it is bonded to a second heat sink body having a larger cross-sectional area mounted to said first heat sink body.

Claim 15

An article of manufacture for mounting an integrated circuit chip, said chip having a first side with a plurality of bonding pads for bonding of a plurality of leads to said chip and a second side, said article comprising: (a) a first heat sink having a first mounting surface adapted for bonding to said second side of said chip; (b) a first mounting means bonding said first mounting surface to said second side of said chip in good heat transfer relation; (c) a second heat sink having a second mounting surface adapted for bonding to said first side; (d) second mounting means including a low temperature alloy for bonding said second mounting surface to said first side of said chip in good heat transfer relation; (e) isolating means for insulating said second mounting means to prevent electrical connection of said chip to said second heat sink; and (f) encapsulating means for encapsulating said chip between said first heat sink and said second heat sink; (g) said first side of said chip having a passivation layer of electrical insulating material deposited thereon and a layer of gold formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said second heat sink.

Claim 16

An article of manufacture for mounting an integrated circuit chip, said chip having a first side with a plurality of bonding pads for bonding of a plurality of leads to said chip and a second side, said article comprising: (a) a first heat sink having a first mounting surface adapted for bonding to said second side of said chip; (b) a first mounting means bonding said first mounting surface to said second side of said chip in good heat transfer relation; (c) a second heat sink having a second mounting surface adapted for bonding to said first side; (d) second mounting means including a low temperature alloy for bonding said second mounting surface to said first side of said chip in good heat transfer relation; (e) isolating means for insulating said second mounting means to prevent electrical connection of said chip to said second heat sink; and (f) encapsulating means for encapsulating said chip between said first heat sink and said second heat sink; (g) said first side of said chip having a passivation layer of electrical insulating material deposited thereon and a layer of gold formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said second heat sink.

Claim 17

The article of claim 12, wherein said second mounting surface is adapted to match said first side of said chip so that when bonded by said second mounting means to said chip said second mounting surface avoids contact with said bonding pads or said leads.

Claim 18

The article of claim 12, wherein said bonding pads are arranged around an outside peripheral of said first side of said chip and said second mounting surface is adapted for bonding to said first side in an area inside the outside peripheral defined by said bonding pads.

Claim 19

The article of claim 12, wherein said isolating means includes a passivation layer formed on said first side of said chip to define a mounting area on said first side to which said second mounting means bonds said second heat sink.

Claim 20

A mounting arrangement for a semiconductor chip having a bottom surface and a top surface with an integrated circuit fashioned thereon, including a plurality of bonding pads disposed around the periphery of said top surface, comprising: (a) a printed circuit substrate having a substantially planar top surface with a bonding pad and circuit lead arrangement formed thereon; (b) means for mounting said semiconductor chip on said substrate in an inverted orientation with said top surface of said chip separated from the top surface of said substrate and including means for electrically connecting said chip bonding pads to said bonding pad and circuit lead arrangement of said substrate; (c) a first heat sink mounted to said bottom surface of said chip and a second heat sink having a first surface mounted rigidly to a portion of said top surface of said chip interior to said bonding pads and a second surface mounted rigidly to said top surface of said substrate, wherein said means for electrically connecting said chip bonding pads to said bonding pad and circuit lead arrangement of the substrate comprises a plurality of flexible connecting lead elements extending outwardly from said bonding pads around the periphery of said top surface of said clip and downwardly to said bonding pad and circuit lead arrangement of the substrate; whereby the flexible connecting lead elements allow mounting of said second heat sink on both said first surface and said second surface and wherein said top surface of said chip has a passivation layer of electrical insulating material deposited thereon and a layer of gold formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said second heat sink.

Claim 21

A mounting arrangement for a semiconductor chip having a bottom surface and a top surface with an integrated circuit fashioned thereon, including a plurality of bonding pads disposed around the periphery of said top surface, comprising: (a) a printed circuit substrate having a substantially planar top surface with a bonding pad and circuit lead arrangement formed thereon; (b) means for mounting said semiconductor chip on said substrate in an inverted orientation with said top surface of said chip separated from the top surface of said substrate and including means for electrically connecting said chip bonding pads to said bonding pad and circuit lead arrangement of said substrate; (c) a first heat sink mounted to said bottom surface of said chip and a second heat sink having a first surface mounted rigidly to a portion of said top surface of said chip interior to said bonding pads and a second surface mounted rigidly to said top surface of said substrate, wherein said means for electrically connecting said chip bonding pads to said bonding pad and circuit lead arrangement of the substrate comprises a plurality of flexible connecting lead elements extending outwardly from said bonding pads around the periphery of said top surface of said clip and downwardly to said bonding pad and circuit lead arrangement of the substrate; whereby the flexible connecting lead elements allow mounting of said second heat sink on both said first surface and said second surface and wherein said top surface of said chip has a passivation layer of electrical insulating material deposited thereon and a layer of gold formed over a portion of said passivation layer interior to said bonding pads to provide a mounting pad for said second heat sink.