High-frequency semiconductor package

Claim 2

A semiconductor device package as in claim 2 wherein said interlaced lead means comprises: a. first metal leads connecting portions of the base region of said transistor chip to the first portion of the top metal layer of said first ceramic member; and b. second metal leads interlaced with said first metal leads connecting portions of the emitter region of said transistor chip to said first contact means.

Claim 3

A semiconductor device package as in claim 1 wherein said first and second metallized ceramic members are of different type ceramics.

Claim 4

A semiconductor device package as in claim 4 wherein said first metallized ceramic member is BeO.

Claim 5

A semiconductor device package as in claim 1 wherein said metal header is Oxygen-free, high conductivity copper.

Claim 6

A semiconductor device package as in claim 1 wherein the bottom surface of said second ceramic member is metallized.

Claim 7

A semiconductor device package as in claim 1 wherein said lead means is interlaced leads.

Claim 8

A semiconductor device package for improving high frequency operation comprising: a. a copper header having first, second and third portions, the second portion separated from the first and third portion by spaced walls and adapted to receive an electrical contacting surface; b. a first metallized ceramic member having top, bottom and side surfaces adapted to be received by the second portion of said copper header and apertures formed in said first metallized ceramic member from the top to the bottom surface, including a first metal layer disposed on the bottom surface connected to said copper header and second and third metal layers disposed on the top surface, the second metal layer integral with said apertures whereby the second metal layer is electrically connected to the first metal layer; c. a second metallized ceramic member having top, bottom and side surfaces including fourth and fifth metal layers disposed on the top and bottom surfaces respectively, the fifth metal layer connected to a part, but not all of, the second metal layer; d. a semiconductor wafer having at least three active regions formed therein secured to the third metal layer whereby one of the active regions is in electrical contact with said third metal layer; e. first contact means for making electrical contact thereto connected to the third metal layer; f. second contact means for making electrical contact thereto connected to the fourth metal layer; g. first lead means for connecting the second of said active regions to said second contact means; and h. second lead means interlaced with said first lead means for connecting the third of said active regions to the portion of the second metal layer not connected to the fifth metal layer.

Claim 9

A semiconductor package as in claim 9 wherein said first and second metallized ceramic members are of different type ceramics.

Claim 10

A semiconductor package as in claim 10 wherein said first metallized member is fabricated of BeO.

Claim 11

A semiconductor package as in claim 10 wherein said second metallized ceramic member is fabricated of aluminum oxide.

Claim 12

A semiconductor package as in claim 9 wherein said semiconductor wafer is a transistor chip.

Claim 13

A semiconductor package as in claim 9 wherein said second metal layer comprises a first portion aligned with a side surface of said first metallized ceramic member and second and third parallel, spaced portions extending from the transverse ends of said first portion, said second and third portions each integral with and disposed within said apertures whereby said first and second metal layers and said apertures are in electrical continuity.

Claim 14

A semiconductor package as in claim 14 wherein said third metal layer is substantially T-shaped and comprises a first portion disposed between the second and third portions of said second metal layer and a cross portion abutting an end of said first portion and transversely extending substantially equidistant on opposed sides of said first portion.

Claim 15

A semiconductor package as in claim 15 wherein said semiconductor wafer is mounted on the first portion of said third metal layer.

Claim 16

A semiconductor package as in claim 9 wherein said first and second lead means are interlaced, stitch bonded metal leads.

Claim 17

An improved package for operating semiconductor devices at high frequencies comprising: a. a substantially oxygen-free copper header having a cavity therein adapted to receive an electrical contacting surface and means for mounting said copper header; b. a first metallized ceramic member having top, bottom and side surfaces and apertures from the top to the bottom surfaces and having a first metal layer disposed on the bottom surface cOnnected to said cavity and second and third metal layers on the top surface, the second metal layer being substantially U-shaped and integral with and disposed around said apertures whereby said first and second metal layers are in electrical continuity, said third metal layer being substantially T-shaped and having perpendicular and cross portions in cooperative relationship with but isolated from said second metal layer; c. a second substantially U-shaped metallized ceramic member having top, bottom and side surfaces and fourth and fifth metal layers disposed on the top and bottom surfaces respectively, said fifth metal layer being connected to only a first portion of said second metal layer leaving a second portion thereof exposed; d. a first metal contact having parallel, spaced extended portions at an end thereof, said extended portions connected to the fourth metal layer whereby said extended portions are on opposed sides of the perpendicular portion of said third metal layer; e. a second metal contact connected to the third metal layer; f. a transistor chip having a body which is the collector region thereof and base and emitter regions which are in a cooperative, interdigitated relationship with each other, said collector region connected to said third metal layer; g. first metal leads connecting fingers of the interdigitated emitter region to each of the extended portions of said first metal contact; h. second metal leads connecting fingers of the interdigitated base region to the exposed second portion of said second metal layer; and i. means for encapsulating said cavity.

Claim 18

A semiconductor package as in claim 18 wherein said first and second metallized ceramic members are fabricated of different ceramics.

Claim 19

A semiconductor package as in claim 19 wherein said first metallized ceramic member is fabricated of BeO.

Claim 20

A semiconductor package as in claim 18 wherein said first and second metal leads are interlaced with each other.