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US4620158A
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PCM signal demodulating circuit
Assignee: Pioneer Corp
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Filing: 1985-08-22
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Granted: 1986-10-28
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Expires: 2005-08-22
Abstract
Abstract A PCM signal demodulating circuit in which a PCM signal corresponding to a code representative of a first sample value obtained by sampling an analog signal with a first sampling frequency is processed to obtain the first sample value, thereby to calculate a pseudo sample value equivalent to a second sample value obtained by sampling the analog signal at a second sampling frequency higher than the first sampling frequency. This is accomplished by passing the PCM signal through a digital filter, a digital-to-analog converter, and a low-pass filter connected in cascade.
Inventors
- 👤 Kenichiro Yasukawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:04
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10527; H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0626; H03M1/0629; H03M1/0631; H03M1/66; H03M1/82; H03M1/822
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
91 words
In a PCM signal demodulating circuit comprising means for processing a PCM signal including a digital signal corresponding to a code representative of a first sample value obtained by sampling an analog signal at a first sampling frequency to obtain said analog signal through demodulation, the improvement wherein said PCM signal demodulating circuit further comprising: means for processing said first sample value to calculate a pseudo sample value equivalent to a second sample value obtained by sampling said analog signal at a second sampling frequency higher than said first sampling frequency.
Claim 2
Dependent Claim
91 words
In a PCM signal demodulating circuit comprising means for processing a PCM signal including a digital signal corresponding to a code representative of a first sample value obtained by sampling an analog signal at a first sampling frequency to obtain said analog signal through demodulation, the improvement wherein said PCM signal demodulating circuit further comprising: means for processing said first sample value to calculate a pseudo sample value equivalent to a second sample value obtained by sampling said analog signal at a second sampling frequency higher than said first sampling frequency.
Claim 3
Dependent Claim
59 words
The PCM signal demodulating circuit of claim 1, wherein said processing means comprises a digital filter, a digital-to-analog converter having an input coupled to an output of said digital filter, an analog low-pass filter having an input coupled to an output of said digital-to-analog converter, and means for supplying clock pulses to said digital filter and said digital-to-analog converter.
Claim 4
Dependent Claim
29 words
The PCM signal demodulating circuit of claim 2, wherein said digital filter functions as a low-pass filter having a cut-off frequency substantially one-fourth a frequency of said clock pulses.
References Cited (Backward Citations)
US4101964A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-27 | 1990-04-28 | 1990-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-27 | 1994-04-28 | 1994-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-27 | 1998-04-28 | 1998-10-28 | $7700.00 | Window Closed / Lapsed |