Patent US4006362A successfully refreshed from Google Patents.
Patent US4619036A successfully refreshed from Google Patents.
US4619036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned low-temperature emitter drive-in
Assignee: Texas Instruments Inc
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Filing: 1984-09-28
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Granted: 1986-10-28
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Expires: 2004-09-28
Abstract
Abstract After the extrinsic base region of a bipolar transistor has been formed, and the emitter contact has been patterned and cut, the emitter dopant is deposited or spun on, and the emitter dopant is then driven in using a short pulse of radiant energy. The necessity for high-temperature annealing of the emitter doping is thereby avoided, and the base doping profile is not disturbed by high-temperature annealing steps.
Inventors
- 👤 Robert H. Havemann
- 👤 Samuel C. Baber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:55
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10P32/14; H10P32/1408; H10P34/00; H10P34/40; H10P34/42; Y; Y10; Y10S; Y10S148/00; Y10S148/01
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
139 words
A process for fabricating integrated circuits comprising bipolar transistors, comprising the steps of: (a) providing a substrate having, at at least predetermined device locations, first conductivity type collector/emitter regions, second conductivity type base regions above said collector/emitter regions, said first conductivity type surface regions above said base regions, all formed in crystalline semiconductor material having a vertically continuous lattice structure through said collector/emitter, intrinsic base, and surface regions; (b) partially covering said surface regions with a patterned protective layer, said patterned protective layer exposing portions of said surface layer; (c) depositing a first-conductivity-type dopant source on said patterned protective layer and the exposed portions of said surface region, and (d) applying transient pulsed radiant heating to said dopant source on the exposed portions of said surface region to form heavily-doped first-conductivity-type emitter/collector regions within portions of said surface region.
Claim 2
Dependent Claim
139 words
A process for fabricating integrated circuits comprising bipolar transistors, comprising the steps of: (a) providing a substrate having, at at least predetermined device locations, first conductivity type collector/emitter regions, second conductivity type base regions above said collector/emitter regions, said first conductivity type surface regions above said base regions, all formed in crystalline semiconductor material having a vertically continuous lattice structure through said collector/emitter, intrinsic base, and surface regions; (b) partially covering said surface regions with a patterned protective layer, said patterned protective layer exposing portions of said surface layer; (c) depositing a first-conductivity-type dopant source on said patterned protective layer and the exposed portions of said surface region, and (d) applying transient pulsed radiant heating to said dopant source on the exposed portions of said surface region to form heavily-doped first-conductivity-type emitter/collector regions within portions of said surface region.
Claim 3
Dependent Claim
28 words
The method of claim 1, further comprising the step of: forming an extrinsic base region in contact with said intrinsic base region, prior to said dopant deposition step.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein said substrate is composed substantially of silicon.
Claim 5
Dependent Claim
12 words
The method of claim 3, wherein said dopant source is metallic antimony.
Claim 6
Dependent Claim
203 words
A process for fabricating integrated circuits comprising bipolar transistors, comprising the steps of: (a) providing a substrate having, at at least predetermined device locations, first conductivity type collector/emitter regions, second conductivity type base regions above said collector/emitter regions, and first conductivity type surface regions above said base regions, all formed in crystalline semiconductor material having a vertically continuous lattice structure through said collector/emitter, intrinsic base, and surface regions; (b) partially covering said surface regions with a patterned protective layer, said patterned protective layer covering predetermined locations of said surface layer where transistors are to be formed; (c) etching, oxidizing, and ion implanting with a second-conductivity-type dopant portions of said surface region exposed by said protective layer to form extrinsic base regions covered by oxide in locations not covered by said protective layer; (d) removing said patterned protective layer and clearing the surface of said surface layer formerly covered by said protective layer; (e) depositing a first-conductivity-type dopant source on said extrinsic base oxide regions and said exposed portions of said surface layer, and (f) applying transient pulsed radiant heating to said dopant source on the exposed portions of said surface region to form heavily-doped first-conductivity-type emitter/collector regions within portions of said surface layer.
Claim 7
Dependent Claim
203 words
A process for fabricating integrated circuits comprising bipolar transistors, comprising the steps of: (a) providing a substrate having, at at least predetermined device locations, first conductivity type collector/emitter regions, second conductivity type base regions above said collector/emitter regions, and first conductivity type surface regions above said base regions, all formed in crystalline semiconductor material having a vertically continuous lattice structure through said collector/emitter, intrinsic base, and surface regions; (b) partially covering said surface regions with a patterned protective layer, said patterned protective layer covering predetermined locations of said surface layer where transistors are to be formed; (c) etching, oxidizing, and ion implanting with a second-conductivity-type dopant portions of said surface region exposed by said protective layer to form extrinsic base regions covered by oxide in locations not covered by said protective layer; (d) removing said patterned protective layer and clearing the surface of said surface layer formerly covered by said protective layer; (e) depositing a first-conductivity-type dopant source on said extrinsic base oxide regions and said exposed portions of said surface layer, and (f) applying transient pulsed radiant heating to said dopant source on the exposed portions of said surface region to form heavily-doped first-conductivity-type emitter/collector regions within portions of said surface layer.
Claim 8
Dependent Claim
28 words
The method of claim 5, further comprising the step of: forming an extrinsic base region in contact with said intrinsic base region, prior to said dopant deposition step.
Claim 9
Dependent Claim
13 words
The method of claim 5, wherein said substrate is composed substantially of silicon.
Claim 10
Dependent Claim
12 words
The method of claim 7, wherein said dopant source is metallic antimony.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-27 | 1990-04-28 | 1990-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-27 | 1994-04-28 | 1994-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-27 | 1998-04-28 | 1998-10-28 | $7700.00 | Window Closed / Lapsed |