Monotonic A/D converter which minimizes circuitry for high order bit conversion

Claim 1

A converter for providing an N bit digital output signal corresponding to an analog input signal, where N is an integer, the most significant X bits of the N bits representing a selected one of a plurality of chords defining a range of possible values of the analog input signal and the least significant (N-X) bits of the N bits representing a selected one of a plurality of steps defining a range of possible step values of the analog input signal within any one of the chords, where X is also an integer, comprising: charge redistribution means for selectively storing a charge proportional to the analog input and selectively redistributing the stored charge in proportion to the N bits, comprising: a plurality of capacitors having first interconnected electrodes and respective second electrodes, for selectively redistributing an amount of the stored charge corresponding to the N bits; a C rung switching network comprising a plurality of C rung switching elements, each coupled between the second electrode of a respective one of the capacitors and a common rail, for coupling the respective one of the second electrodes to the common rail in response to a predetermined one of a plurality of first select signals; and a C rail switching network comprising a plurality of C rail switching elements, each coupled between the second electrodes of respective successive pairs of the capacitors, for decoupling, in response to the first select signals corresponding to each successive pair of capacitors, the second electrode of a selected one of the capacitors from the second electrodes of adjacent capacitors; voltage divider means coupled to the charge redistribution means for selectively further redistributing the stored charge corresponding to the (N-X) bits, comprising: resistance means coupled between first and second reference voltage terminals, for developing on each of a plurality of step nodes a predetermined step voltage; and an R rung switching network comprising a plurality of R rung switching elements, each coupled between a respective one of the step nodes and the common rail, for coupling, in response to a predetermined one of a plurality of second select signals, one of the step voltages or said first reference voltage terminal to the common rail; a plurality of select logic means coupled to the R rung and C rung switching networks for providing the pluralities of first and second select signals, each of said select signals having a logic high or low value in response to a predetermined one of a plurality of decode control signals; and a single one of X or one of (N-X) decoder, whichever is greater, coupled to the select logic means for providing the decode control signals in response to an approximation of the digital output signal.