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US4616362A
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Logic for calculating bit error rate in a data communication system
Assignee: RCA Corp
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Filing: 1984-07-19
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Granted: 1986-10-07
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Expires: 2004-07-19
Abstract
Abstract A system for determining the bit error rate in a communication system comprising logic for generating a stream of data bits, bit extracting logic for periodically extracting N consecutive bits after the occurrence of every Mth bit, where the N consecutive bits are divided into a group of A bits and a group of C bits, where A and C are equal integers, and a single B bit is positioned between the group of A and C bits, where M>>A, where the N bits can be any combination of binary 1's and 0's. Logic extracts and stores a finely quantized sample of the B bit of each group of N bits. An adder adds an auxiliary group of X bits to the N bits to form a memory address consisting of A, B, C, and X bits. A plurality of memories each has storage locations for a single finely quantized B bit sample. Each memory further is selectable by a unique combination of the binary bits A+B+C with any given storage location in each memory being accessible by various combinations of the X bits. Appropriate logic by a predetermined algorithm calculates the current probability of bit rate error.
Inventors
- 👤 Leonard N. Schiff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:03
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
150 words
In a communication system for transmitting and receiving a high speed stream of data bits, a method of determining the current bit error rate but not the specific bits that are in error and comprising the steps of: extracting and storing consecutive sequences of A, B, and C data bits at known and identifiable time intervals, where A and C are an equal small number of bits and B is a single bit; extracting and storing finely quantized sample of the amplitude of the center portion of the B data bit by auxiliary means shown in FIG. 1; storing in memory the finely quantized center amplitudes of the B bit for each different combination of binary 1's and 0's for each different sequence of bits A, B, and C; calculating from known and predetermined algorithms the current bit error rate of the system from the information stored in said memory.
Claim 2
Dependent Claim
150 words
In a communication system for transmitting and receiving a high speed stream of data bits, a method of determining the current bit error rate but not the specific bits that are in error and comprising the steps of: extracting and storing consecutive sequences of A, B, and C data bits at known and identifiable time intervals, where A and C are an equal small number of bits and B is a single bit; extracting and storing finely quantized sample of the amplitude of the center portion of the B data bit by auxiliary means shown in FIG. 1; storing in memory the finely quantized center amplitudes of the B bit for each different combination of binary 1's and 0's for each different sequence of bits A, B, and C; calculating from known and predetermined algorithms the current bit error rate of the system from the information stored in said memory.
Claim 3
Dependent Claim
198 words
In a communication system employing a high speed stream of data bits, a method of determining the current bit error rate and comprising the steps of: extracting and storing consecutive sequences of N+1 data bits at identifiable time intervals spaced apart M bits where M>>N, where N is an even number, and where N+1 can be any combination of binary 1's and 0's; digitizing and storing a finely quantized sampling of a data bit B selected from the center of each of said N+1 sequences to form a sequence of bits N/2, B, and N/2, which equals N+1 data bits, where B=1 bit; providing a plurality of 2.sup.(N+1) memories with each memory selectable by a corresponding one of the combination of bits 2.sup.(N+1) and each have having a memory location for storing the finely quantized value of the B bit; entering the finely quantized values of the B bit into successive memory locations of the corresponding memory as the corresponding combination of N+1 bits are extracted from said high speed stream of data bits; and calculating from a predetermined algorithm and the stored values of the finely quantized B bit samples the bit error rate of the system.
Claim 4
Dependent Claim
198 words
In a communication system employing a high speed stream of data bits, a method of determining the current bit error rate and comprising the steps of: extracting and storing consecutive sequences of N+1 data bits at identifiable time intervals spaced apart M bits where M>>N, where N is an even number, and where N+1 can be any combination of binary 1's and 0's; digitizing and storing a finely quantized sampling of a data bit B selected from the center of each of said N+1 sequences to form a sequence of bits N/2, B, and N/2, which equals N+1 data bits, where B=1 bit; providing a plurality of 2.sup.(N+1) memories with each memory selectable by a corresponding one of the combination of bits 2.sup.(N+1) and each have having a memory location for storing the finely quantized value of the B bit; entering the finely quantized values of the B bit into successive memory locations of the corresponding memory as the corresponding combination of N+1 bits are extracted from said high speed stream of data bits; and calculating from a predetermined algorithm and the stored values of the finely quantized B bit samples the bit error rate of the system.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-06 | 1990-04-07 | 1990-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-06 | 1994-04-07 | 1994-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-06 | 1998-04-07 | 1998-10-07 | $7700.00 | Window Closed / Lapsed |