Pipelined programmable charge domain device

Claim 1

A pipelined programmable charge domain device for multiplying a succession of sampled analog signals by associated multiple bit digital word coefficients, the throughput rate of said device being equal to the clock rate of said device, comprising: a semiconductor substrate having electrodes insulatively disposed on said substrate to which signal potentials are applied for inducing wells in said substrate for the storage and propagation of packets of charge in said wells; a plurality of cascaded charge splitter stages formed in said substrate; each of said charge splitter stages having first and second charge splitter wells of substantially equal charge storage capacity, first and second charge accumulator wells, and charge transfer means for channelling equal parts of a charge packet applied thereto to its first and second charge splitter wells, for selectively channelling a charge packet in its second charge splitter well to either its first or its second charge accumulator well in accordance with the value of a bit of a digital word coefficient applied, for channelling equal parts of a charge packet in its first splitter well to the first and second charge splitter wells in the next one of said stages, and for channelling charge packets in its first and second accumulator wells to the first and second accumulator wells respectively in the next one of said stages; means during successive clock cycles of said device for introducing a charge packet representative of an analog input signal to the first and second charge splitter wells in the first one of said plurality of cascaded charge splitter stage; means during said successive clock cycles for receiving ordered bits of a digital word coefficient for delayed application to the charge transfer means of like-ordered ones of said plurality of cascaded charge splitter stages, the application of said bits of a digital word coefficient being delayed at each stage of said plurality of cascaded splitter stages by a number of clock cycles equal to the ordered number of the stage, whereby synchronism is maintained between an applied input signal and its associated digital word coefficient; and charge combiner means coupled to the first and second accumulator wells of the last one of said plurality of charge splitter stages for providing an output signal whose value corresponds to the difference in the magnitudes of the charge packets stored in said charge combiner means.