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US4615017A
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Memory controller with synchronous or asynchronous interface
Assignee: International Business Machines Corp
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Filing: 1983-09-19
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Granted: 1986-09-30
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Expires: 2003-09-19
Abstract
Abstract A common memory interfacing circuit and method for coupling a memory to either a synchronous bus or an asynchronous bus. Synchronizing means are provided for synchronizing memory request signals with a local clock when the interfacing circuit is coupled to an asynchronous bus. The interface circuit responds to signals from the memory when internal memory operation has been completed and generates an acknowledge signal to send to the requesting bus. To simplify the common interface circuit, a synchronous protocol for information exchange between system components is made similar to an asynchronous protocol.
Inventors
- 👤 David E. Finlay
- 👤 Kent S. Norgren
- 👤 Frankie S. Shook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:57
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
223 words
An interface circuit for connecting a bus system with memory controller means to supply a memory access request signal from said bus system to said memory controller means, said controller means for carrying out internal memory operations in accordance with said memory access request signal and for generating a response signal when those operations are complete, said interface circuit connected to receive said response signal and for supplying said response signal to said bus system, said interface circuit connected to either a synchronous bus system or an asynchronous bus system, said interface circuit comprising: switch means for supplying a signal indicative of the type of bus system to which said interface circuit is connected, for passing a synchronous mode signal if synchronous type is indicated and for passing an asynchronous mode signal if asynchronous type is indicated; receiving means for receiving said memory access request signal from said bus system; synchronizing means connected to receive said memory access request signal from said receiving means and for synchronizing said memory access request signal with the timing of said controller means; and logic circuit means connected between said synchronizing means and said controller means and also connected to said switch means for receiving the synchronous and asynchronous mode signals from said switch means and for passing said memory access request signal to said controller means.
Claim 2
Dependent Claim
223 words
An interface circuit for connecting a bus system with memory controller means to supply a memory access request signal from said bus system to said memory controller means, said controller means for carrying out internal memory operations in accordance with said memory access request signal and for generating a response signal when those operations are complete, said interface circuit connected to receive said response signal and for supplying said response signal to said bus system, said interface circuit connected to either a synchronous bus system or an asynchronous bus system, said interface circuit comprising: switch means for supplying a signal indicative of the type of bus system to which said interface circuit is connected, for passing a synchronous mode signal if synchronous type is indicated and for passing an asynchronous mode signal if asynchronous type is indicated; receiving means for receiving said memory access request signal from said bus system; synchronizing means connected to receive said memory access request signal from said receiving means and for synchronizing said memory access request signal with the timing of said controller means; and logic circuit means connected between said synchronizing means and said controller means and also connected to said switch means for receiving the synchronous and asynchronous mode signals from said switch means and for passing said memory access request signal to said controller means.
Claim 3
Dependent Claim
55 words
The interface circuit of claim 1 further including: second logic circuit means for generating a transfer acknowledge signal; and second receiving means for receiving a response signal from said controller upon completion of memory internal operation and for passing said response signal to said second logic means for the generation of said transfer acknowledge signal.
Claim 4
Dependent Claim
104 words
The interface circuit of claim 2 wherein said second logic circuit means is connected to receive said synchronous and asynchronous mode signals and wherein said second receiving means is comprised of: first response means for receiving said response signal from said controller means and passing said response signal to said second logic circuit means for generating said transfer acknowledge signal when said synchronous mode signal is present; and second response means for receiving said response signal from said controller means and passing said response signal to said second logic circuit means for generating said transfer acknowledge signal when said asynchronous mode signal is present.
Claim 5
Dependent Claim
42 words
The interface circuit of claim 1 wherein said logic circuit means is also connected directly between said receiving means and said controller means for passing said memory access request signal directly to said controller means when said synchronous mode signal is present.
Claim 6
Independent Claim
171 words
The method of connecting memory circuits to either a synchronous bus or an asynchronous bus through a common interface circuit for receiving memory access request signals and responding with an acknowledge signal, comprising: setting a switch means in said interface circuit to generate a synchronous mode signal if said memory circuits are connected to a synchronous bus and to generate an asynchronous mode signal if said memory circuits are connected to an asynchronous bus; receiving said memory access request signal in a decoder circuit from said synchronous bus or from said asynchronous bus whichever type signal is presented; and passing said memory access request signal to logic means and then to a state machine controller for performance of internal memory operation in accordance with said memory access request signal and in accordance with a read/write command signal, said passing step including a synchronizing step if in asynchronous mode to synchronize said memory access request signal to a local memory clock signal, and not including said synchronizing step if in synchronous mode.
Claim 7
Independent Claim
171 words
The method of connecting memory circuits to either a synchronous bus or an asynchronous bus through a common interface circuit for receiving memory access request signals and responding with an acknowledge signal, comprising: setting a switch means in said interface circuit to generate a synchronous mode signal if said memory circuits are connected to a synchronous bus and to generate an asynchronous mode signal if said memory circuits are connected to an asynchronous bus; receiving said memory access request signal in a decoder circuit from said synchronous bus or from said asynchronous bus whichever type signal is presented; and passing said memory access request signal to logic means and then to a state machine controller for performance of internal memory operation in accordance with said memory access request signal and in accordance with a read/write command signal, said passing step including a synchronizing step if in asynchronous mode to synchronize said memory access request signal to a local memory clock signal, and not including said synchronizing step if in synchronous mode.
Claim 8
Dependent Claim
134 words
The method of claim 5 wherein said interface circuit also provides common circuit means for interfacing said memory circuits with either a synchronous bus or an asynchronous bus, said common circuit means for generating an acknowledgement signal to said memory access request signal upon completion of internal memory operation in accordance with said memory access request signal and in accordance with a read/write command signal, said method further including the steps of: receiving a first response signal from said state machine controller; passing said first response signal to second logic means for generating said acknowledgement signal when connected to a synchronous bus; receiving a second response signal from said state machine controller; and passing said second response signal to said second logic means for generating said acknowledgement signal when connected to an asynchronous bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-29 | 1990-03-31 | 1990-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-29 | 1994-03-31 | 1994-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-29 | 1998-03-31 | 1998-09-30 | $7700.00 | Window Closed / Lapsed |