Coaxial semiconductor package

Claim 2

A semiconductor package comprising: a first, electrically conducting bus; a second, electrically conducting bus spaced from and generally surrounding said first bus in approximate concentric relation thereto and being electrically isolated therefrom; and a plurality of generally equally angularly spaced semi-conductors in the space between said buses, each said semiconductor having at least first and second electrodes; said first electrodes being electrically connected to said first bus and said second electrodes being electrically connected to said second bus.

Claim 3

The semiconductor package of claim 1 wherein one of said first and second electrodes are in essentially direct contact with the associated bus, and further including pressurizing means for pressing said one of said first and second electrodes against the associated bus.

Claim 4

The semiconductor package of claim 2 wherein said pressurizing means supply an approximately equal pressing force against each of said semiconductors.

Claim 5

The semiconductor package of claim 1 wherein said semiconductors have at least three electrodes, including control electrodes, and a third bus within and generally concentric to at least said second bus, said third bus being a control bus adapted to receive a control signal for controlling the conduction of said semiconductors and being electrically connected to said control electrodes.

Claim 6

The semiconductor package of claim 4 wherein said control bus is within and concentric to both said first and second buses.

Claim 7

The semiconductor package of claim 1 wherein said second bus includes coolant passages in heat exchange relation with said semiconductors.

Claim 8

A semiconductor package comprising: a circular tube-like housing formed of electrically conducting material and having a radially inner wall; a plurality of generally equally angularly spaced recesses in said wall; a semiconductor wafer having at least three electrodes, including a control electrode, in each of said recesses and having two electrodes including said control electrode, electrically isolated from said housing and the third electrode connected to said housing; means within said housing for biasing said wafers into their respective recesses; a central conductor within said housing in generally concentric relation thereto and electrically isolated therefrom; and electrically conductive means of approximately equal length extending from said central conductor to respective ones of said control electrodes and electrically isolated from said housing; said biasing means including additional electrically conductive means in contact with the remaining electrode of each semiconductors and electrically isolated from said housing, said central conductor, and said extending means.

Claim 9

A semiconductor package comprising: a circular tube-like housing formed of electrically conducting material and having a radially inner wall; a plurality of generally equally angularly spaced recesses in said wall; a semiconductor wafer having at least three electrodes, including a control electrode, in each of said recesses and having two electrodes including said control electrode, electrically isolated from said housing and the third electrode connected to said housing; means within said housing for biasing said wafers into their respective recesses; a central conductor within said housing in generally concentric relation thereto and electrically isolated therefrom; and electrically conductive means of approximately equal length extending from said central conductor to respective ones of said control electrodes and electrically isolated from said housing; said biasing means including additional electrically conductive means in contact with the remaining electrode of each semiconductors and electrically isolated from said housing, said central conductor, and said extending means.

Claim 10

The semiconductor package of claim 7 wherein heat exchangers are disposed in the bottoms of each of said recesses and are abutted by the respective third electrode of the associated semiconductor wafer to cool the same, said heat exchangers establishing an electrical connection between said third electrodes and said housing.

Claim 11

The semiconductor package of claim 8 wherein said heat exchangers include an insert having an axial coolant passage.

Claim 12

The semiconductor package of claim 8 wherein each said recess is stepped, having a radially outer narrow portion separated from a radially inner wider portion by a shoulder, said narrow portion serving as a coolant manifold, said heat exchangers each comprising a perforated plate abutting said shoulder and a channeled plate having channels aligned with and facing the perforations in said perforated plate interposed between said perforate plate and said wafer.

Claim 13

The semiconductor package of claim 7 wherein said biasing means acts radially between said central conductor and said wafer.

Claim 14

The semiconductor package of claim 7 wherein said biasing means comprise sets of springs, each set acting against two adjacent wafers along a chord of the housing.

Claim 15

The semiconductor package of claim 12 wherein two of said sets act against each wafer.

Claim 16

The semiconductor package of claim 13 further including force equalizing means disposed between said sets and said wafers to assure that an approximately equal biasing force is applied to each of said wafers.