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US4611387A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for producing NPN type lateral transistors

Assignee: Conexant Systems LLC
•
Filing: 1985-04-08
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Granted: 1986-09-16
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Expires: 2005-04-08
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Abstract

Abstract The invention provides a unique VLSI dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate. The support is necessary while orthogonal slots are provided permitting access to opposed sides of the active regions for doping n+ from each end, which n+ is driven in from both sides to provide an n+p n+ emitter-base-collector transistor active region to which electrical connections are applied using conventional techniques providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Inventors

  • 👤 Sidney I. Soclof

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 11:32
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/061; H10D10/60; H10P; H10P30/00; H10P30/20; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/061; H10W10/10; H10W10/17; H10W10/181

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 181 words
A method for forming an array of NPN-type lateral transistors in a silicon substrate doped P-type, wherein each transistor is formed comprising the following steps: masking the substrate to outline a pair of boundary regions for each semi-array including therein a plurality of active regions to become transistors; slotting the substrate in said boundary regions to a given depth; etching away the substrate via said slots sufficiently to separate the semi-arrays of active regions from the substrate except at spaced apart supporting locations therealong; oxidizing the substrate and semi-arrays to at least substantially completely oxidize the peripheries of the semi-arrays; slotting the substrate orthogonally to the first mentioned slots to provide second slots with orthogonal pairs of slots defining individual transistor active regions for the respective transistors; doping the regions defined by orthogonal pairs of slots N+ via corresponding edges of the second slots and driving in the N+ doping until the width of the N+ doped driven-in dimensions respectively exceed 1 micron; and, establishing electrical connections to the outer N+ regions, and inner P region of the substrate doped P-type.
Claim 2
Independent Claim 181 words
A method for forming an array of NPN-type lateral transistors in a silicon substrate doped P-type, wherein each transistor is formed comprising the following steps: masking the substrate to outline a pair of boundary regions for each semi-array including therein a plurality of active regions to become transistors; slotting the substrate in said boundary regions to a given depth; etching away the substrate via said slots sufficiently to separate the semi-arrays of active regions from the substrate except at spaced apart supporting locations therealong; oxidizing the substrate and semi-arrays to at least substantially completely oxidize the peripheries of the semi-arrays; slotting the substrate orthogonally to the first mentioned slots to provide second slots with orthogonal pairs of slots defining individual transistor active regions for the respective transistors; doping the regions defined by orthogonal pairs of slots N+ via corresponding edges of the second slots and driving in the N+ doping until the width of the N+ doped driven-in dimensions respectively exceed 1 micron; and, establishing electrical connections to the outer N+ regions, and inner P region of the substrate doped P-type.
Claim 3
Dependent Claim 15 words
The method of claim 1, wherein: said etching is accomplished by orientation dependent etching fluid.
Claim 4
Independent Claim 19 words
The method of claims 1 or 2 wherein: each active region is supported from the substrate by substrate oxide.
Claim 5
Dependent Claim 27 words
The method of claim 3, wherein: the upper surface of the substrate which is slotted is <100> oriented with the surfaces remaining after etching being <111> oriented.
Claim 6
Independent Claim 24 words
The method of claims 1 or 2 wherein: the active regions are supported from the substrate by webs of oxide along the top thereof.

References Cited (Backward Citations)

US4419150A Cited
US4435899A Cited
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US4522682A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-09-15 1990-03-17 1990-09-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-09-15 1994-03-17 1994-09-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-09-15 1998-03-17 1998-09-16 $7700.00 Window Closed / Lapsed

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