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US4435899A
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US
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Method of producing lateral transistor separated from substrate by intersecting slots filled with substrate oxide
Assignee: Conexant Systems LLC
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Filing: 1982-12-16
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Granted: 1984-03-13
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Expires: 2002-12-16
Abstract
Abstract The invention is a transistor or array thereof and method for producing same in sub-micron dimensions on a silicon substrate doped P or N type by forming slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become a plurality of transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divide the semi-arrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation. Each transistor may further comprise a doped region called P or N doping extending into and across the top of the base region to reduce space region contact resistance and to provide an electron reflecting potential barrier. Each transistor may further comprise a doped skin of either P or N doping to force electrons or holes toward the center of the base region.
Inventors
- 👤 Sidney I. Soclof
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:04
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/184; H10D10/00; H10D10/60; H10P; H10P30/00; H10P30/20; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/096; Y10S148/115; Y10S148/143; Y10S148/168
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
170 words
A method for producing an array of sub-micron dimensioned NPN type lateral transistors formed in a silicon substrate doped P-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; N+ doping each of said active regions through the inner opposed second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original P substrate comprising the base regions; further oxidizing said substrate to fill in said orthogonal slots and insure total peripheral oxide isolation of each transistor active region; and forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 2
Independent Claim
170 words
A method for producing an array of sub-micron dimensioned NPN type lateral transistors formed in a silicon substrate doped P-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; N+ doping each of said active regions through the inner opposed second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original P substrate comprising the base regions; further oxidizing said substrate to fill in said orthogonal slots and insure total peripheral oxide isolation of each transistor active region; and forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 3
Dependent Claim
37 words
A method in accordance with claim 1, comprising: further P+ doping a region extending into and across the top of the base region to reduce base region contact resistance and to provide a hole deflecting potential barrier.
Claim 4
Independent Claim
26 words
A method in accordance with claims 10 or 2, comprising: further providing a P+ doped skin to force holes toward the center of the base region.
Claim 5
Independent Claim
170 words
A method for producing an array of sub-micron dimensioned PNP type lateral transistors formed in a silicon substrate doped N-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; P+ doping each of said active regions through the inner opposed second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original N substrate comprising the base regions; further oxidizing said substrate to fill in said orthogonal slots and insure total peripheral oxide insulation of each transistor active region; and forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 6
Independent Claim
170 words
A method for producing an array of sub-micron dimensioned PNP type lateral transistors formed in a silicon substrate doped N-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; P+ doping each of said active regions through the inner opposed second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original N substrate comprising the base regions; further oxidizing said substrate to fill in said orthogonal slots and insure total peripheral oxide insulation of each transistor active region; and forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 7
Dependent Claim
37 words
A method in accordance with claim 4, comprising: further N+ doping a region extending into and across the top of the base region to reduce base region contact resistance and to provide a hole deflecting potential barrier.
Claim 8
Independent Claim
26 words
A method in accordance with claims 13 or 5, comprising: further providing a N+ doped skin to force holes toward the center of the base region.
Claim 9
Independent Claim
195 words
A method for producing an array of sub-micron dimensioned lateral transistors formed in a silicon substrate doped P type for forming an NPN type transistor and doped N type for forming a PNP type transistor, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; doping each of said active regions through the inner opposed second sidewalls using N doping for P doped substrate and P doping for N doped substrate; driving in said doping to comprise emitter and collector regions on respective sides of the original substrate comprising the base regions; further oxidizing said substrate to fill in said orthogonal slots and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 10
Independent Claim
195 words
A method for producing an array of sub-micron dimensioned lateral transistors formed in a silicon substrate doped P type for forming an NPN type transistor and doped N type for forming a PNP type transistor, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; doping each of said active regions through the inner opposed second sidewalls using N doping for P doped substrate and P doping for N doped substrate; driving in said doping to comprise emitter and collector regions on respective sides of the original substrate comprising the base regions; further oxidizing said substrate to fill in said orthogonal slots and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 11
Dependent Claim
50 words
A method in accordance with claim 7, comprising: further doping a region extending into and across the top of the base region by using N doping for an N substrate and P doping for a P substrate to reduce base region contact resistance and to provide a deflecting potential barrier.
Claim 12
Dependent Claim
37 words
A method in accordance with claim 7 or 17, comprising: further doping the skin to force carriers toward the center of the base region by using P+ doping for P substrate and N+ doping for N substrate.
Claim 13
Dependent Claim
27 words
The method of claim 7, wherein: said substrate is P doped; and, said doping by way of the second sidewalls is N+ to provide an N+PN+ transistor.
Claim 14
Dependent Claim
30 words
The method of claim 7, wherein: said substrate is N doped; and said doping by way of the second sidewalls is P+, followed by N+ to provide an N+P+NN+ transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1987-03-13 | 1987-09-12 | 1988-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-13 | 1991-09-12 | 1992-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-13 | 1995-09-12 | 1996-03-13 | $7700.00 | Window Closed / Lapsed |