US4608751A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making dynamic memory array
Assignee: Texas Instruments Inc
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Filing: 1984-08-07
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Granted: 1986-09-02
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Expires: 2004-08-07
Abstract
Abstract A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:19
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
104 words
A method of making a plurality of dynamic semiconductor memory cells of the one-transistor type at a face of a semiconductor body, comprising the steps of: applying a layer of conductive material on said face overlying and separated from a plurality of cell areas by insulator, each cell area including a transistor area and a capacitor area, opening a plurality of windows in said layer, each window being over one of said transistor areas, applying a plurality of conductive strips on said face over said layer but insulated therefrom, said strips extending into said windows to form gates of transistors at said transistor areas.
Claim 2
Independent Claim
104 words
A method of making a plurality of dynamic semiconductor memory cells of the one-transistor type at a face of a semiconductor body, comprising the steps of: applying a layer of conductive material on said face overlying and separated from a plurality of cell areas by insulator, each cell area including a transistor area and a capacitor area, opening a plurality of windows in said layer, each window being over one of said transistor areas, applying a plurality of conductive strips on said face over said layer but insulated therefrom, said strips extending into said windows to form gates of transistors at said transistor areas.
Claim 3
Dependent Claim
20 words
A method according to claim 1 wherein the semiconductor body is P-type silicon and the conductive material is polycrystalline silicon.
Claim 4
Dependent Claim
26 words
A method according to claim 2 wherein said layer is patterned to define a bias gate for a capacitor which will partially underlie the conductive strips.
Claim 5
Dependent Claim
33 words
A method according to claim 3 wherein said conductive strips are metal and said coating separates said metal from said face except at said windows where a thin gate oxide underlies the metal.
Claim 6
Dependent Claim
30 words
A method according to claim 4 wherein a coating of chick thermal field oxide is formed on said face before applying said layer, except in the capacitor and transistor areas.
Claim 7
Dependent Claim
45 words
A method according to claim 5 wherein an array of rows and columns of said cells is formed at said face, and the metal includes a plurality of parallel strips of metal, each strip forming the gates for a plurality of cells in a row.
Claim 8
Dependent Claim
22 words
A method according to claim 1 wherein said window is laterally spaced along the face away from both edges of said layer.
Claim 9
Independent Claim
70 words
A method of making a semiconductor device comprising the steps of: applying a layer of conductive material over a face of a semiconductor body to form an electrode overlying a first semiconductor region, opening a window in layer over said first semiconductor region, and applying a conductive strip to said face over said layer but insulated therefrom, the strip extending into said window to form another electrode of the device.
Claim 10
Independent Claim
70 words
A method of making a semiconductor device comprising the steps of: applying a layer of conductive material over a face of a semiconductor body to form an electrode overlying a first semiconductor region, opening a window in layer over said first semiconductor region, and applying a conductive strip to said face over said layer but insulated therefrom, the strip extending into said window to form another electrode of the device.
Claim 11
Dependent Claim
26 words
A method according to claim 8 wherein the conductive material in polycrystalline silicon and a thin insulator separates said strip from the face in said window.
Claim 12
Dependent Claim
33 words
A method according to claim 9 wherein conductive strip is metal and the step of applying includes patterning the metal to define an elongated metallic strip forming a transistor gate at said window.
Claim 13
Dependent Claim
32 words
A method according to claim 10 wherein the step of patterning the metal includes leaving a plurality of elongated strips as row lines for an array of rows and columns of cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |