US3874955A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing an mos integrated circuit
Assignee: Panasonic Holdings Corp
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Filing: 1973-03-15
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Granted: 1975-04-01
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Expires: 1993-03-15
Abstract
Abstract A method of manufacturing an MOS integrated circuit by utilizing a self-alignment technique is provided, wherein a capacitor is fabricated independently of other circuit elements. The capacitor is composed of a preliminary diffused region, a silicon dioxide layer and a gate electrode section having at least a portion thereof laid on top of the preliminary diffused region. The capacitor produced in accordance with this method is positively separated from other circuit elements and it may be used, for example, as an auxiliary storage capacitor for an inverter circuit to prevent the lowering of the output signal.
Inventors
- 👤 Shigeru Arita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; H10B; H10B20/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/80; H10D84/811; H10D84/813; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/053; Y10S148/122
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
120 words
A METHOD OF MANUFACTURING AN MOS INTEGRATED CIRCUIT BY UTILIZING THE SELF-ALIGNMENT TECHNIQUE COMPRISING THE STEPS OF: FORMING INTO A PRESELECTED PORTION OF A SILICON SUBSTRATE OF ONE SEMICONDUCTIVITY TYPE OF PRELIMINARY DIFFUSED REGION OF THE OTHER SEMICONDUCTIVITY TYPE OPPOSITE TO THAT OF SAID SILICON SUBSTRATE, FORMING AT LEAST ONE GATE SECTION COMPOSED OF A GATE OXIDE FILM AND A GATE ELECTRODE ON SAID SILICON SUBSTRATE SO THAT AT LEAST OF PORTION OF SAID GATE SECTION ASSOCIATED WITH SAID PRELIMINARY DIFFUSED REGION IS PLACED ON SAID PRELIMINARY DIFFUSED REGION, AND FORMING A PLURALITY OF DIFFUSED REGIONS SO THAT DRAIN REGION AND SOURCE REGION ARE PROVIDED ON THE SIDES OF EACH OF SAID GATE SECTIONS, WHEREBY EACH OF SAID GATE SEC-
Claim 2
Independent Claim
120 words
A METHOD OF MANUFACTURING AN MOS INTEGRATED CIRCUIT BY UTILIZING THE SELF-ALIGNMENT TECHNIQUE COMPRISING THE STEPS OF: FORMING INTO A PRESELECTED PORTION OF A SILICON SUBSTRATE OF ONE SEMICONDUCTIVITY TYPE OF PRELIMINARY DIFFUSED REGION OF THE OTHER SEMICONDUCTIVITY TYPE OPPOSITE TO THAT OF SAID SILICON SUBSTRATE, FORMING AT LEAST ONE GATE SECTION COMPOSED OF A GATE OXIDE FILM AND A GATE ELECTRODE ON SAID SILICON SUBSTRATE SO THAT AT LEAST OF PORTION OF SAID GATE SECTION ASSOCIATED WITH SAID PRELIMINARY DIFFUSED REGION IS PLACED ON SAID PRELIMINARY DIFFUSED REGION, AND FORMING A PLURALITY OF DIFFUSED REGIONS SO THAT DRAIN REGION AND SOURCE REGION ARE PROVIDED ON THE SIDES OF EACH OF SAID GATE SECTIONS, WHEREBY EACH OF SAID GATE SEC-
Claim 3
Dependent Claim
27 words
A method according to claim 1, wherein said MOS integrated circuit, is an inverter circuit, and said capacitor is an auxiliary storage capacitor for said inverter circuit.
References Cited (Backward Citations)
US3408543A
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US3387286A
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US3604107A
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US3745383A
Cited
US3740732A
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US3747200A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-31 | 1978-09-30 | 1979-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-31 | 1982-09-30 | 1983-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-31 | 1986-09-30 | 1987-04-01 | $7700.00 | Window Closed / Lapsed |