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US4606011A
Expired / Lapsed
US
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Single transistor/capacitor semiconductor memory device and method for manufacture
Assignee: Toshiba Corp
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Filing: 1985-10-24
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Granted: 1986-08-12
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Expires: 2005-10-24
Abstract
Abstract A semiconductor memory device and a method for manufacturing such a device provides increased capacitance for memory cells of a dynamic RAM by using the top and sides of island regions formed in the substrate.
Inventors
- 👤 Masashi Wada
- 👤 Shigeyoshi Watanabe
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:00
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/37; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/014; H10W10/10; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
182 words
A semiconductor memory comprising: (a) a plurality of memory cells formed on a substrate of a first conductivity type, each said memory cell including (i) an MOS transistor having a gate and a conduction path, and (ii) an MOS capacitor coupled to one side of said conduction path, said MOS capacitor including (aa) a first electrode of a second conductivity type formed in said substrate in contact with said one side of said conduction path, said first electrode having at least three sides, (bb) a thin insulation film formed on said first electrode to cover said three sides of said first electrode, (cc) a second electrode formed on said thin insulation film and opposite each of said at least three faces, and (dd) a device protection film formed on said second electrode; (b) a plurality of word lines each coupled to the gates of ones of said plurality of MOS transistors in a different row; and (c) a plurality of bit lines each coupled to the other side of the conduction paths of ones of said MOS transistors in a different column.
Claim 2
Dependent Claim
182 words
A semiconductor memory comprising: (a) a plurality of memory cells formed on a substrate of a first conductivity type, each said memory cell including (i) an MOS transistor having a gate and a conduction path, and (ii) an MOS capacitor coupled to one side of said conduction path, said MOS capacitor including (aa) a first electrode of a second conductivity type formed in said substrate in contact with said one side of said conduction path, said first electrode having at least three sides, (bb) a thin insulation film formed on said first electrode to cover said three sides of said first electrode, (cc) a second electrode formed on said thin insulation film and opposite each of said at least three faces, and (dd) a device protection film formed on said second electrode; (b) a plurality of word lines each coupled to the gates of ones of said plurality of MOS transistors in a different row; and (c) a plurality of bit lines each coupled to the other side of the conduction paths of ones of said MOS transistors in a different column.
Claim 3
Dependent Claim
53 words
The semiconductor memory of claim 1 wherein said memory cells are formed on island regions of said substrate, each island region having a top and at least two sides and wherein said at least three sides of said electrode include portions of the top and at least two sides of said island regions.
Claim 4
Dependent Claim
16 words
The semiconductor memory of claim 2 wherein two memory cells are formed on each island region.
Claim 5
Dependent Claim
58 words
The semiconductor memory of claim 2 wherein said island regions are separated by grooves and wherein said memory further comprises a device separation region of said first conductivity type at the bottom of each said groove and a field isolation film filling part of said groove, said field isolation film having a top surface which is substantially flat.
Claim 6
Dependent Claim
34 words
The semiconductor memory of claim 1 wherein said thin insulation film includes a thermal oxide film, wherein said device protection film comprises SiO 2 , and wherein said word lines comprise polycrystalline silicon film.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-11 | 1990-02-10 | 1990-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-11 | 1994-02-10 | 1994-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-11 | 1998-02-10 | 1998-08-12 | $7700.00 | Window Closed / Lapsed |