FSK demodulator with high noise immunity digital phase detector

Claim 2

A detector, for use with means for receiving, splitting, phase shifting, and mixing with a local oscillator signal a received modulated signal to produce binary in-phase and binary quadrature phase signals respectively at in-phase and quadrature phase output, said detector comprising in combination: first flip flop means, connected to said quadrature phase output, for clocking said quadrature phase signal on the leasing edge of said in-phase signal; second flip flop means, connected to said in-phase output, for clocking said in-phase signal on the leading edge of said quadrature phase signal; third flip flop means, connected to said quadrature phase output, for clocking said quadrature phase signal on the trailing edge of said in-phase signal; fourth flip flop means, connected to said in-phase output, for clocking said in-phase signal on the trailing edge of said quadrature phase signal; and averaging means, connected to said first, second, third, and fourth flip flop means, for averaging the output signals of said first, second, third, and fourth flip flop means.

Claim 3

The detector of claim 1, wherein said averaging means includes first, second, third, and fourth resistors, each of said resistors having one terminal respectively connected to said first, second, third, and fourth flip flop means, and the second terminals of said resistors being mutually connected.

Claim 4

The detector of claim 2, wherein said averaging means further includes a capacitor, connected to said second terminals of said resistors.

Claim 5

A receiver for detecting a received modulated signal, said receiver comprising in combination: means for receiving, splitting, phase shifting, and mixing with a local oscillator signal said received modulated signal to produce binary in-phase and binary quadrature phase signals, said quadrature generator means having in-phase and quadrature phase outputs; first and second flip flops, each having an input connected to said in-phase output and each having a clock input connected to said quadrature phase output, wherein said first flip flop is leading edge triggered and said second flip flop is trailing edge triggered; third and fourth flip flops, each having an input connected to said quadrature phase output and each having a clock input connected to said in-phase output, wherein said third flip flop is leading edge triggered and said fourth flip flop is trailing edge triggered; first, second, third, and fourth resistors, each of said resistors having one terminal respectively connected to an output of said first, second, third, and fourth flip flops, and the second terminals of said resistors being mutually connected; and a capacitor connected to the mutually connected terminals of said resistors.

Claim 6

A receiver for detecting a received modulated signal, said receiver comprising in combination: means for receiving, splitting, phase shifting, and mixing with a local oscillator signal said received modulated signal to produce binary in-phase and binary quadrature phase signals, said quadrature generator means having in-phase and quadrature phase outputs; first and second flip flops, each having an input connected to said in-phase output and each having a clock input connected to said quadrature phase output, wherein said first flip flop is leading edge triggered and said second flip flop is trailing edge triggered; third and fourth flip flops, each having an input connected to said quadrature phase output and each having a clock input connected to said in-phase output, wherein said third flip flop is leading edge triggered and said fourth flip flop is trailing edge triggered; first, second, third, and fourth resistors, each of said resistors having one terminal respectively connected to an output of said first, second, third, and fourth flip flops, and the second terminals of said resistors being mutually connected; and a capacitor connected to the mutually connected terminals of said resistors.

Claim 7

The receiver of claim 4, further comprising a comparator, connected to the mutually connected terminals of said resistors.

Claim 8

The receiver of claim 4, wherein said quadrature generator means includes a quadrature coupler having an input for receiving said received signal.

Claim 9

A receiver for detecting a received signal, said receiver comprising in combination: a quadrature coupler having an input, wherein said received signal is coupled to said input of said quadrature coupler; a cascaded first mixer, first filter, and first limiter, said first mixer having an input connected to the in-phase output of said quadrature coupler; a cascaded second mixer, second filter, and second limiter, said second mixer having an input connected to the quadrature phase output of said quadrature coupler; first and second D flip flops, each having a D input connected to said first limiter and each having a clock input connected to said second limiter, wherein said first D flip flop is leading edge triggered and said second D flip flop is trailing edge triggered; third and fourth D flip flops, each having a D input connected to said second limiter and each having a clock input connected to said first limiter, wherein said third D flip flop is leading edge triggered and said fourth D flip flop is trailing edge triggered; a voltage comparator; a capacitor connector to an input of said voltage comparator; first, second, third, and fourth resistors each having one terminal respectively connected to the Q-NOT output of said first D flip flop, the Q output of said second D flip flop, the Q output of said third D flip flop, and the Q-NOT output of said fourth D flip flop, the second terminals of said resistors being connected to said input of said voltage comparator.

Claim 10

A receiver for detecting a received signal, said receiver comprising in combination: a quadrature coupler having an input, wherein said received signal is coupled to said input of said quadrature coupler; a cascaded first mixer, first filter, and first limiter, said first mixer having an input connected to the in-phase output of said quadrature coupler; a cascaded second mixer, second filter, and second limiter, said second mixer having an input connected to the quadrature phase output of said quadrature coupler; first and second D flip flops, each having a D input connected to said first limiter and each having a clock input connected to said second limiter, wherein said first D flip flop is leading edge triggered and said second D flip flop is trailing edge triggered; third and fourth D flip flops, each having a D input connected to said second limiter and each having a clock input connected to said first limiter, wherein said third D flip flop is leading edge triggered and said fourth D flip flop is trailing edge triggered; a voltage comparator; a capacitor connector to an input of said voltage comparator; first, second, third, and fourth resistors each having one terminal respectively connected to the Q-NOT output of said first D flip flop, the Q output of said second D flip flop, the Q output of said third D flip flop, and the Q-NOT output of said fourth D flip flop, the second terminals of said resistors being connected to said input of said voltage comparator.