Phase logic demodulator

Claim 2

In a phase-shift keying, suppressed-carrier communication system, a phase logic demodulator comprising: (a) a first AND gate; (b) a second AND gate; (c) means for impressing a phase modulated signal simultaneously on both of said AND gates; (d) an injection locked oscillator having two outputs, one of which is 180° phase shifted with respect to the other; (e) means for impressing the output of said first AND gate on said oscillator and for impressing one of the outputs of said oscillator on said first AND gate; (f) means including 180° phase shift for connecting the output of said second AND gate on said oscillator and for impressing the second output of said oscillator back on said second AND gate; and (g) an envelope detector connected to the outputs of both of said AND gates for generating the data.

Claim 3

A demodulator as defined in claim 1 wherein each of said AND gates consists of a differential amplifier pair.

Claim 4

A demodulator as defined in claim 2 wherein said injection locked oscillator consists of a differential amplifier pair having two outputs 180° out of phase with respect to each other.

Claim 5

A demodulator as defined in claim 1 wherein each of said AND gates consists of a transferred electron device having a cathode and an anode, wherein the cathode of a first AND gate and the cathode of the other AND gate is coupled to said injection locked oscillator.

Claim 6

A demodulator as defined in claim 4 wherein said injection locked oscillator consists of a transferred electron device having a cathode and an anode and wherein the cathode of the transferred electron device representing said oscillator is connected to said first AND gate and its anode to said other AND gate.

Claim 7

In a quadriphase-shift-keying, suppressed-carrier communication system, a demodulator comprising: (a) a first, a second, a third, and a fourth AND gate; (b) an injection locked oscillator having four outputs, each being shifted in phase with respect to another by 90°; (c) means for impressing a phase-shifted input signal simultaneously on each of said four AND gates; (d) means including a 90° phase shifter for connecting the output of said first AND gate to a first input of said injection locked oscillator; (e) means including a 270° phase shifter for connecting the output of said second AND gate to a second input of said oscillator; (f) means for connecting the output of said third AND gate to third input of said oscillator; (g) means including a 180° phase shifter for connecting the output of said fourth AND gate to a fourth input of said oscillator; (h) means for connecting a reference or zero phase output of said oscillator to said third AND gate; (i) means for connecting the 90° phase shifted output of said oscillator to said first AND gate; (j) means for connecting the 270° phase shifted output of said oscillator to said second AND gate; (k) means for connecting the 180° phase-shifted output of said oscillator to said fourth AND gate, whereby one of said AND gates provides an output if the input signal is in phase with the oscillator wave impressed thereon; and (l) an envelope detector having four inputs connected to the outputs of said AND gates for developing the output data.

Claim 8

In a quadriphase-shift-keying, suppressed-carrier communication system, a demodulator comprising: (a) a first, a second, a third, and a fourth AND gate; (b) an injection locked oscillator having four outputs, each being shifted in phase with respect to another by 90°; (c) means for impressing a phase-shifted input signal simultaneously on each of said four AND gates; (d) means including a 90° phase shifter for connecting the output of said first AND gate to a first input of said injection locked oscillator; (e) means including a 270° phase shifter for connecting the output of said second AND gate to a second input of said oscillator; (f) means for connecting the output of said third AND gate to third input of said oscillator; (g) means including a 180° phase shifter for connecting the output of said fourth AND gate to a fourth input of said oscillator; (h) means for connecting a reference or zero phase output of said oscillator to said third AND gate; (i) means for connecting the 90° phase shifted output of said oscillator to said first AND gate; (j) means for connecting the 270° phase shifted output of said oscillator to said second AND gate; (k) means for connecting the 180° phase-shifted output of said oscillator to said fourth AND gate, whereby one of said AND gates provides an output if the input signal is in phase with the oscillator wave impressed thereon; and (l) an envelope detector having four inputs connected to the outputs of said AND gates for developing the output data.

Claim 9

In a phase-shift keying, suppressed-carrier communication system, a demodulator comprising: (a) a first and a second AND circuit; (b) each of said AND circuits including a first differential amplifier pair having two outputs 180° out of phase with respect to each other; (c) an envelope detector for each of said AND gates, each of said envelope detectors including a second differential amplifier pair having two inputs connected to the two outputs of said first differential amplifier pair 180° out of phase, and a detector coupled between said second differential amplifier pair; (d) a low pass filter coupled to each of said envelope detectors; (e) an injection locked oscillator comprising a third differential amplifier pair having two outputs 180° out of phase with respect to each other; (f) means for impressing the output of each of said AND circuits being 180° out of phase with respect to each other on said third differential amplifier pair; (g) means for injecting the outputs of said oscillator on each of said AND circuits; and (h) means for impressing a biphase key-shifted input signal on each of said AND circuits.

Claim 10

In a phase-shift keying, suppressed-carrier communication system, a demodulator comprising: (a) a first and a second AND circuit; (b) each of said AND circuits including a first differential amplifier pair having two outputs 180° out of phase with respect to each other; (c) an envelope detector for each of said AND gates, each of said envelope detectors including a second differential amplifier pair having two inputs connected to the two outputs of said first differential amplifier pair 180° out of phase, and a detector coupled between said second differential amplifier pair; (d) a low pass filter coupled to each of said envelope detectors; (e) an injection locked oscillator comprising a third differential amplifier pair having two outputs 180° out of phase with respect to each other; (f) means for impressing the output of each of said AND circuits being 180° out of phase with respect to each other on said third differential amplifier pair; (g) means for injecting the outputs of said oscillator on each of said AND circuits; and (h) means for impressing a biphase key-shifted input signal on each of said AND circuits.

Claim 11

A demodulator as defined in claim 7 wherein said differential amplifier pairs consist each of two transistors.

Claim 12

A demodulator as defined in claim 8 wherein each of said AND circuits includes a fourth differential amplifier pair consisting of two transistors coupled to said first differential amplifier pair.

Claim 13

A demodulator as defined in claim 8 wherein an RC circuit is connected to the emitters of each of the four transistors of said first and fourth differential amplifier pair.

Claim 14

A demodulator as defined in claim 9 wherein an emitter follower transistor is coupled to the input of each of said fourth differential amplifier pair of each of said AND gates.

Claim 15

A demodulator as defined in claim 9 wherein a pair of oppositely poled diodes is provided between each of the two transistors of said fourth differential amplifier pair and the following transistor of said first amplifier pair for each of said AND gates.

Claim 16

A demodulator as defined in claim 9 wherein a first transistor connected as a constant current source is coupled to second transistor connected as a constant current source is coupled to said first differential amplifier pair and to said fourth differential amplifier pair for each AND circuit.

Claim 17

A demodulator as defined in claim 8 wherein a transistor connected as a constant current source is coupled to said second differential amplifier pair.

Claim 18

A demodulator as defined in claim 8 wherein a transistor connected as a constant current source is connected to each of said three differential amplifier pairs.

Claim 19

A demodulator as defined in claim 8 wherein a first emitter follower amplifier is connected to the inputs of each of said third differential amplifier pair for impressing thereon the two outputs of said second AND gate which are 180° out of phase, and wherein an additional emitter follower transistor is coupled to the inputs of each of said third differential amplifier pair for impressing thereon the two outputs of said first AND gate which are 180° out of phase, thereby to provide a feedback path for said oscillator.

Claim 20

A demodulator as defined in claim 16 wherein said injection-locked oscillator generates two outputs 180° out of phase with respect to each other and means for impressing each of said outputs on one of said AND gates to complete the feedback path for said oscillator.