Demodulating circuitry for pulse rate modulation data reproduction

Claim 2

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations representating data of one nature by the presence thereof intermediate the timing manifestations and representing data of another nature by the absence of any signal manifestations intermediate of said timing manifestations, comprising an input terminal to which electric manifestations of pulse rate modulated rate are applied, a data output terminal at which electric manifestations of demodulated data are delivered, measuring circuitry coupled to said input terminal for producing an interval manifestation representative of the interval between successive signal manifestations while storing at least one associated reference manifestation representative of the interval between preceding signal manifestations, comparing circuitry coupled to said measuring circuitry for comparing each interval manifestation with at least one associated reference manifestation, for thereby decoding said information as timing information on data of said one nature, circuit connections between said comparing circuitry and said data output terminal, and circuitry connected between said comparing circuitry and said measuring circuitry for determining intervals between timing manifestations only regardless of the presence or absence of other manifestations intermediate thereof.

Claim 3

Demodulating circuitry for pulse rate modulation data reproduction accommodating variations in the modulating-trough-demodulating cycle having a predetermined ratio of pulse rate for differentiating between data of different nature comprising, an input terminal at which electric manifestations of pulse rate modulated data are applied, a data output terminal at which electric manifestations of demodulated data of one nature are delivered, circuitry coupled to said input terminal for measuring intervals between successive pairs of manifestations of data, circuitry coupled to said measuring circuitry for retrospectively comparing the measurements of successive intervals between said manifestations of data, circuitry coupled to said comparing circuitry for determining binary data of one nature on recognition that the comparisons of the measurements of said intervals are unequal, a circuit connection between said determining circuitry and said data output terminal, and electric connections for measuring intervals between manifestations of timing information only despite the presence or absence of other manifestations.

Claim 4

Demodulating circuitry for pulse rate modulation data reproduction accommodating variations in the modulating-trough-demodulating cycle having a predetermined ratio of pulse rate for differentiating between data of different nature comprising, an input terminal at which electric manifestations of pulse rate modulated data are applied, a data output terminal at which electric manifestations of demodulated data of one nature are delivered, circuitry coupled to said input terminal for measuring intervals between successive pairs of manifestations of data, circuitry coupled to said measuring circuitry for retrospectively comparing the measurements of successive intervals between said manifestations of data, circuitry coupled to said comparing circuitry for determining binary data of one nature on recognition that the comparisons of the measurements of said intervals are unequal, a circuit connection between said determining circuitry and said data output terminal, and electric connections for measuring intervals between manifestations of timing information only despite the presence or absence of other manifestations.

Claim 5

Demodulating circuitry for pulse rate modulation data reproduction as defined in claim 2 and wherein said predetermined ratio is 2:1.

Claim 6

Demodulating circuitry for pulse rate modulation data reproduction as defined in claim 2 and wherein said predetermined ratio lies in a range of ratios between one-third and two-thirds of the longer interval between said electric manifestations.

Claim 7

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 1, and wherein said measuring circuitry comprises A ramp voltage generating circuit effective for preserving the ramp voltage upon the appearance of a successive electric manifestation, another ramp voltage generating circuit, and circuitry responsive to the appearance of a successive nanifestation for alternating operation of said ramp voltage generating circuits in generating and storing interval manifestations.

Claim 8

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 2, wherein said measuring circuitry comprises two analog generating circuits and said comparing circuitry comprises at least one analog comparing circuit.

Claim 9

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally sspaced timing manifestations and other signal manifestations as defined in claim 2 and wherein said comparing circuitry comprises two analog comparing circuits and a voltage dividing arrangement for determining the presence of intervals of said predetermined ratio.

Claim 10

Demodulating circuitry for pulse rate modulation data reproduction accommodating variations in the modulating-through-demodulating cycle having a predetermined ratio of pulse rate for differentiating between data of different nature comprising, an input terminal to which electric manifestations of pulse rate modulated data are applied, a data output terminal at which electric manifestations of demodulated data are delivered, an AND gating circuit having an input lead connected to said input terminal and having another input lead and an output lead, a bistable flip-flop circuit having a triggering lead connected to said AND gating circuit output lead and having complementary output leads, time interval measuring circuitry connected to said complementary output leads for measuring two periods between pulse transitions appearing at said output lead of said AND gating circuit, comparing circuitry connected to said measuring circuitry for comparing the measurements and having an output terminal, a connection from said output terminal of said measuring circuitry to said other input lead of said AND gating circuit, a keyed flip-flop circuit having a keying terminal connected to said signal input terminal, having two triggering terminals coupled to said comparing circuitry in opposite phase relationship, and having complementary output terminals, a circuit connection between one of said complementary output terminals and said data output terminal, and circuit connections between said AND gating circuit and said comparing circuitry.

Claim 11

Demodulating circuitry for pulse rate modulation data reproduction accommodating variations in the modulating-through-demodulating cycle having a predetermined ratio of pulse rate for differentiating between data of different nature comprising, an input terminal to which electric manifestations of pulse rate modulated data are applied, a data output terminal at which electric manifestations of demodulated data are delivered, an AND gating circuit having an input lead connected to said input terminal and having another input lead and an output lead, a bistable flip-flop circuit having a triggering lead connected to said AND gating circuit output lead and having complementary output leads, time interval measuring circuitry connected to said complementary output leads for measuring two periods between pulse transitions appearing at said output lead of said AND gating circuit, comparing circuitry connected to said measuring circuitry for comparing the measurements and having an output terminal, a connection from said output terminal of said measuring circuitry to said other input lead of said AND gating circuit, a keyed flip-flop circuit having a keying terminal connected to said signal input terminal, having two triggering terminals coupled to said comparing circuitry in opposite phase relationship, and having complementary output terminals, a circuit connection between one of said complementary output terminals and said data output terminal, and circuit connections between said AND gating circuit and said comparing circuitry.

Claim 12

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 8 and wherein said measuring circuitry comprises two ramp voltage generating circuits individually connected to the complementary output leads of said bistable flip-flop circuit and having reset terminals, and output terminals connected to said comparing circuitry, two AND gating circuits having input leads individually connected to said complementary output leads of said complementary output leads of said bistable flip-flop circuit, input leads connected in common to said strobe terminal and output leads, two differentiating circuits connected individually between the output leads of said AND gating circuits and the reset leads of the ramp voltage generating circuits.

Claim 13

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 8 and wherein said comparing circuitry comprises a pair of gating circuits coupled to said measuring circuitry, a differential amplifying circuit having input terminals individuAlly coupled to said gating circuits and an output terminal, and connections, including an inverting circuit between the output terminal of said difference amplifying circuit and the triggering terminals of said keyed flip-flop circuit.

Claim 14

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 2 and wherein said measuring circuitry comprises a pair of AND gating circuits having input terminals individually connected to the complementary output leads of said bistable flip-flop circuit input terminals connected in common to said strobe terminal and output leads, a pair of holding ramp generating circuits having terminals individually connected to the output leads of said pair of AND gating circuits, reference voltage terminals, initial condition reset terminals, and output terminals connected to said comparing circuitry.

Claim 15

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 8 and wherein said comparing circuitry comprises two differential amplifying circuits having input terminals connected in common to said measuring circuitry, other input terminals, and output terminals, a voltage dividing circuit having terminals connected to said measuring circuitry, said intermediate taps connected individually to the other input terminal of said differential amplifying circuits, an AND gating circuit having an input terminal connected to one of said differential amplifying circuits, another input of said differential amplifying circuit, and having an output terminal, connections including another inverting circuit to the triggering terminals of said keyed flip-flop circuit.

Claim 16

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 2 and wherein said measuring circuitry comprises digital counting circuitry and digital control logical circuitry connected to said comparing circuitry.

Claim 17

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations as defined in claim 13 and wherein said measuring circuitry also comprises a pair of digital register circuits and a digital arithmetic circuit connected to said counting circuit for determining and holding an upper limit and a lower limit value for comparison with the current count in said digital counting circuitry in said comparing circuitry.

Claim 18

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations comprising, an input terminal to which electric manifestations of pulse rate modulated data are applied, an output terminal at which electric manifestations of demodulated data are delivered, circuitry comprising a source of substantially uniformly spaced time interval electric impulses, control logical circuitry connected to said input terminal and to said source of electric impulses for generating a series of sequential control pulses, circuitry connected to said source and coupled to said logical control circuitry for counting the number of electric impulses between electric timing manifestations, digital impulse translating circuitry coupled to said counting circuitry for deriving at least one value of a count proportional to a preceding interval count for determining data of said one nature, circuitry connected to said counting circuitry and to said digital impulses translation circuitry for comparing the count in said counting circuitry within the count in said impulse tranSlating circuitry for determining the presence of data of said one nature, and an electric connection between said comparing circuitry and said control logical circuitry for counting impulses between electric timing manifestations only despite the presence or absence of other manifestations.

Claim 19

Demodulating circuitry for decoding information conveyed by a train of signal manifestations of nominally equally spaced timing manifestations and other signal manifestations comprising, an input terminal to which electric manifestations of pulse rate modulated data are applied, an output terminal at which electric manifestations of demodulated data are delivered, circuitry comprising a source of substantially uniformly spaced time interval electric impulses, control logical circuitry connected to said input terminal and to said source of electric impulses for generating a series of sequential control pulses, circuitry connected to said source and coupled to said logical control circuitry for counting the number of electric impulses between electric timing manifestations, digital impulse translating circuitry coupled to said counting circuitry for deriving at least one value of a count proportional to a preceding interval count for determining data of said one nature, circuitry connected to said counting circuitry and to said digital impulses translation circuitry for comparing the count in said counting circuitry within the count in said impulse tranSlating circuitry for determining the presence of data of said one nature, and an electric connection between said comparing circuitry and said control logical circuitry for counting impulses between electric timing manifestations only despite the presence or absence of other manifestations.

Claim 20

Demodulating circuitry for pulse rate modulation data reproduction as defined in claim 15, and wherein said digital impulse translating circuitry comprises circuitry for deriving a range of values intermediate the limits of a preceding interval count.

Claim 21

Demodulating circuitry for pulse rate modulation data reproduction as defined in claim 16, and wherein said comparing circuitry includes two magnitude comparator circuits, an OR gating circuit connected to the HI and EQUALS output terminals of one of said magnitude comparator circuits, a bistable flip-flop circuit having set terminals coupled to said OR gating circuit reset terminals, and complementary output terminals at which data levels are available, an AND gating circuit connected to the LO terminals of said one magnitude comparator circuit and to the HI terminals of said other comparator circuit and having the output connected to the reset terminals of said bistable flip-flop circuit.

Claim 22

Demodulating circuitry for pulse rate modulation data reproduction as defined in claim 17, and wherein said digital in pulse translating circuitry includes arithmetic circuitry coupled to said counting circuit, a pair of registers connected to said arithmetic circuitry and to said magnitude comparator circuits there being connections to said control logical circuitry for transferring numerical representations from said arithmetic circuitry to said registers relative to said predetermined ratio of data representation.

Claim 23

Demodulating circuitry for pulse rate modulation data reproduction as defined in claim 17, and wherein said digital impulse translating circuitry includes another binary counting circuit having an input terminal and having a reset terminal connected to said logical control circuitry, an AND gating circuit and a dividing circuit interposed in series between said impulse generating circuit and the input terminal of said other counting circuit, a down counting circuit connected to the first said counting circuit for receiving a count therefrom under control of said control logical circuitry and having an input lead connected to the output lead of said AND gating circuit, another OR gating circuit coupled to a number of stages of said down counting circuit for deriving a predetermined number for application of another lead of said AND gating circuit, and two connections between the said counting circuit, and said magnitude comparator circuits at stages representing a difference in numbers obtainable as by shifting the counter a prearranged number of stages.

Claim 24

Demodulating circuitry for pulse rate modulation data reproduction as defined in claim 19, and wherein said dividing circuit is arranged to divide by a factor of three and said other counting circuit is arranged for shifting by a factor of two.