US3758870A — Digital demodulator

Claim 1

Independent Claim 143 words

A demodulator for detecting binary information which is encoded in successive bauds of a modulated carrier signal, said demodulator comprising sampling means for samplIng said carrier signal to produce a stream of quantized carrier signal samples f(zT), where T is the sampling interval in the time domain and - infinity < OR = z < OR = infinity ; a discrete Fourier transform filter for filtering said f(zT) samples to produce an I + jQ product value for each value of z, where I and Q are the Fourier components; means for rotating said I and Q Fourier components by n pi /4 radians to produce I'' and Q'' components, where n is an integer; and means responsive to said I, Q, I'' and Q'' components for adjusting the response of said filter to match the timing and phase of the carrier signal.

Claim 2

Dependent Claim 143 words

A demodulator for detecting binary information which is encoded in successive bauds of a modulated carrier signal, said demodulator comprising sampling means for samplIng said carrier signal to produce a stream of quantized carrier signal samples f(zT), where T is the sampling interval in the time domain and - infinity < OR = z < OR = infinity ; a discrete Fourier transform filter for filtering said f(zT) samples to produce an I + jQ product value for each value of z, where I and Q are the Fourier components; means for rotating said I and Q Fourier components by n pi /4 radians to produce I'' and Q'' components, where n is an integer; and means responsive to said I, Q, I'' and Q'' components for adjusting the response of said filter to match the timing and phase of the carrier signal.

Claim 3

Dependent Claim 96 words

The invention as set forth in claim 1 and further including a timing network which produces a first timing signal; wherein said filter includes means for producing local reference signals in response to said timing signal, means for multiplying said signal samples by said reference values to form product values, and means for accumulating said product values to form said I + jQ product value for each value of z; wherein said adjusting means adjusts the frequency of said first timing signal to synchronize the phase of the local reference signal with the carrier signal phase.

Claim 4

Dependent Claim 52 words

The invention as set forth in claim 2 wherein said adjusting means includes means for taking the modulo two sum of the signs of said I, Q, I'' and Q'' components during each baud; and means for adjusting said timing signal frequency in accordance with the value of said modulo two sum.

Claim 5

Dependent Claim 73 words

The invention as set forth in claim 1 and further including a timing network which produces a first timing signal; wherein said filter responds to said first timing signal to produce said I + jQ product value for each value of z; and wherein said adjusting means adjusts the frequency of said timing signal so as to achieve the match of the filter response to the timing and phase of the carrier signal.

Claim 6

Dependent Claim 49 words

The invention as set forth in claim 4 wherein said adjusting means includes means for taking the modulo two sum of the signs of said I, Q, I'' and Q'' components; and means for adjusting said timing signal frequency in accordance with the value of said modulo two sum.

Claim 7

Dependent Claim 153 words

Invention as set forth in claim 5 wherein said adjusting means further includes an averaging circuit which averages the modulo two sum values over a number of bauds so as to emit at its output a correction signal whenever the average attains either a maximum or minimum value; and means responsive to said averaging circuit output and to said modulo two sum during each baud to generate a code having a first value in the absence of said correction signal and either a second or a third value in response to said correction signal in accordance with the value of the modulo two sum which is in time coincidence with the correction signal; and wherein said timing network responds to said code to produce the first timing signal at a normal operating frequency for said first value and at relatively higher and lower frequencies in response to the second and third values, respectively.

Claim 8

Dependent Claim 66 words

The invention as set forth in claim 6 wherein said first timing signal is produced once during each sampling interval T and has a pulse width which is small compared to T; wherein said code generating means responds to the absence of said first timing signal to generate said first code value and to the presence thereof to generate either said first, second or third values.

Claim 9

Dependent Claim 175 words

A demodulator for detecting binary information which is encoded in successive bauds of a modulated carrier signal, said demodulator comprising sampling means for sampling said carrier signal to produce a stream of quantized carrier signal samples f(zT), where T is the sampling interval in the time domain and - Infinity < or = z < or = Infinity ; a timing and synchronization network including an internal baud timing chain which periodically produces a baud timing signal at the baud rate of said carrier signal; a discrete Fourier transform filter responsive to a first one of said timing signals for filtering said f(zT) samples to produce an I + jQ product value for each value of z, where I and Q are the Fourier components; means for rotating said I and Q Fourier components by n pi /4 radians to produce I'' and Q'' components, where n is an integer; and means responsive to said I, Q, I'' and Q'' components for synchronizing said internal baud timing chain with the bauds of the carrier signal.

Claim 10

Dependent Claim 175 words

A demodulator for detecting binary information which is encoded in successive bauds of a modulated carrier signal, said demodulator comprising sampling means for sampling said carrier signal to produce a stream of quantized carrier signal samples f(zT), where T is the sampling interval in the time domain and - Infinity < or = z < or = Infinity ; a timing and synchronization network including an internal baud timing chain which periodically produces a baud timing signal at the baud rate of said carrier signal; a discrete Fourier transform filter responsive to a first one of said timing signals for filtering said f(zT) samples to produce an I + jQ product value for each value of z, where I and Q are the Fourier components; means for rotating said I and Q Fourier components by n pi /4 radians to produce I'' and Q'' components, where n is an integer; and means responsive to said I, Q, I'' and Q'' components for synchronizing said internal baud timing chain with the bauds of the carrier signal.

Claim 11

Dependent Claim 91 words

The invention as set forth in claim 8 wherein said synchronizing network includes means responsive to the change in signs of either or both of the I and Q components and the I'' and Q'' components from one value of z to the next so as to produce axis crossing signals; means responsive to said baud timing signal and to said axis crossing signal to produce early and late pulses; and means responsive to said early and late pulses for advancing and retarding, respectively, the occurrence of said baud timing signal.

Claim 12

Dependent Claim 111 words

The invention as set forth in claim 9 wherein said internal baud timing chain includes means for producing clock pulses at the sample rate; and a bidirectional counting network responsive to said clock pulses to count in a first direction so as to divide the frequency of said pulses to produce said baud timing signal; and wherein said means for advancing and retarding includes a gate responsive to each said early pulse to insert an additional pulse in the stream of said clock pulses and further includes a connection for coupling said late pulses to said counting network such that the counting network counts in the other direction in response thereto.

Claim 13

Dependent Claim 108 words

The invention as set forth in claim 10 wherein said means for producing early and late pulses includes first gating means responsive to said baud timing signal for producing early and late axis crossing signals; an averaging network for averaging said early and late axis crossing signals over a number of values of z so as to emit at its output either an early or a late correction signal whenever the average attains either a maximum or a minimum value; and selection means operable to select either said early and late axis crossing signals or said early and late correction signals as said early and late pulses, respectively.

Claim 14

Dependent Claim 37 words

The invention as set forth in claim 11 wherein said selection means initially selects said early and late axis crossing signals for a predetermined number of bauds and thereafter normally selects the early and late correction signals.

Claim 15

Dependent Claim 84 words

The invention as set forth in claim 12 wherein said means for producing said axis crossing signals includes means for detecting said charges in sign for each value of z; storage means for storing each said detected change in sign for one sample interval T; and means responsive to said detection means and said storage means for correlating the detected changes in sign for a current value of z and the most previous value of z so as to produce said axis crossing signals.

Claim 16

Dependent Claim 84 words

The invention as set forth in claim 9 wherein said means for producing said axis crossing signals includes means for detecting said changes in sign for each value of z; storage means for storing each said detected change in sign for one sample interval T; and means responsive to said detection means and said storage means for correlating the detected changes in sign for a current value of z and the most previous value of z so as to produce said axis crossing signals.

Claim 17

Dependent Claim 111 words

The invention as set forth in claim 14 wherein said internal baud timing chain includes means for producing clock pulses at the sample rate; and a bidirectional counting network responsive to said clock pulses to count in a first direction so as to divide the frequency of said pulses to produce said baud timing signal; and wherein said means for advancing and retarding includes a gate responsive to each said early pulse to insert an additional pulse in the stream of said clock pulses and further includes a connection for coupling said late pulses to said counting network such that the counting network counts in the other direction in response thereto.

Claim 18

Dependent Claim 108 words

The invention as set forth in claim 15 wherein said means for producing early and late pulses includes; first gating means responsive to said baud timing signal for producing early and late axis crossing signals; an averaging network for averaging said early and late axis crossing signals over a number of values of z so as to emit at its output either an early or a late correction signal whenever the average attains either a maximum or a minimum value; and selection means operable to select either said early and late axis crossing signals to said early and late correction signals as said early and late pulses, respectively.

Claim 19

Dependent Claim 37 words

The invention as set forth in claim 16 wherein said selection means initially selects said early and late axis crossing signals for a predetermined number of bauds and thereafter normally selects the early and late correction signals.

Claim 20

Dependent Claim 41 words

The invention as set forth in claim 8 and further including a data decoding network responsive to the sign values of the I, Q, I'' and Q'' components for detecting and decoding the binary information encoded upon the modulated carrier signal.

Claim 21

Dependent Claim 159 words

The invention as set forth in claim 18 wherein said carrier signal modulation is four phase differentially coherent phase shift keying where the phase vectors have differential phases of plus or minus 45* or plus or minus 135*; wherein said data decode network includes a digital phase shifting network responsive to said baud timing signal to operate upon the sign values of the I, Q, I'' and Q'' components to phase shift the modified four phase vector I + jQ by 45* so as to form its equivalent straight four phase I + jQ vector, where straight four phase vectors have differential phases of 0*, 180* or plus or minus 90*; a phase vector detection network which detects the differential phase of the equivalent I + jQ vector from one baud to the next; and decoding means responsive to the detected differential phase to form a bilevel signal indicative of the binary information encoded upon said modulated carrier signal.

Claim 22

Dependent Claim 75 words

The invention as set forth in claim 19 wherein said digital phase shifting network includes a three stage binary counter responsive to said baud timing signal to cycle through its count values at the baud rate; and a group of selection devices responsive to said count values to select the combination of said I, Q, I'' and Q'' sign values and/or their complements, which combination yields the equivalent I + jQ straight four phase vector.

Claim 23

Dependent Claim 44 words

The invention as set forth in claim 20 and further including a temporary storage device which is arranged to be loaded in response to said baud timing signal when said sign values and which has its outputs coupled to said group of selection devices.

Claim 24

Dependent Claim 21 words

The invention as set forth in claim 7 wherein said carrier signal modulation is four phase differentially coherent phase shift keying.

Claim 25

Dependent Claim 71 words

The invention as set forth in claim 22 wherein said modulation is of the modified four phase type in which the phase vectors have differential phases of plus or minus 45* or plus or minus 135*; and wherein said adjusting means further includes means for complementing said modulo two sum during every other baud such that said adjusting means responds to the modulo two sum and its complement during alternate bauds.

Claim 26

Dependent Claim 21 words

The invention as set forth in claim 17 where said carrier signal modulation is four phase differentially coherent phase shift keying.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-09-10	1977-03-12	1977-09-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-09-10	1981-03-12	1981-09-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-09-10	1985-03-12	1985-09-11	$7700.00	Window Closed / Lapsed

Digital demodulator

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