US4603384A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system with multiple memories and program counter
Assignee: Texas Instruments Inc
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Filing: 1985-09-18
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Granted: 1986-07-29
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Expires: 2005-09-18
Abstract
Abstract A memory for generating data signals responsive to a select signal, a means for generating an increment signal responsive to particular ones of the data signals, a counter for selectively outputting the select signal corresponding to a stored count value, and a means for selectively incrementing the stored count value in the counter responsive to the increment signal. In a preferred embodiment, the data processing system includes means for selectively generating first and second enable signals responsive to particular ones of the data signals and includes, a first counter for selectively generating a select signal corresponding to a stored count value responsive to the first enable signal and a second counter for selectively generating the select signal corresponding to a stored count value responsive to the second enable signal. The data processing system further includes a processing circuit for performing operations responsive to the data signals, input means for selectively outputting signals responsive to input stimuli, and output means for selectively providing an output representation responsive to an output representation signal.
Inventors
- 👤 George L. Brantingham
- 👤 Ashok H. Someshwar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
404 words
A data processing system comprising: memory means having an input and an output, said memory means providing a first series of instruction output signals in response to first address select signals applied to the input of said memory means and a second series of instruction output signals in response to second address select signals applied to the input of said memory means; first counter means coupled to said memory means and producing said first address select signals to be applied to the input of said memory means; second counter means coupled to said memory means and producing said second address select signals to be applied to the input of said memory means; enabling means interposed between the output of said memory means and a first input of each of said first and second counter means in coupled relationship therewith for producing one of either a first enable signal to said first counter means in response to a first predetermined instruction output signal from said memory means or a second enable signal to said second counter means in response to a second predetermined instruction output signal from said memory means; said first enable signal allowing said first counter means to produce said first address select signals applied to the input of said memory means to produce said first series of instruction output signals from said memory means, and said second enable signal allowing said second counter means to produce said second address select signals applied to the input of said memory means to produce said second series of instruction output signals from said memory means; and incrementing means coupled between the output of said memory means and a second input of each of said first and second counter means for producing a first increment signal to said first counter means in response to a third predetermined instruction output signal from said memory means or a second increment signal to said second counter means in response to a fourth predetermined instruction output signal from said memory means; said first increment signal incrementing said first counter when said first enable signal is present and said second increment signal incrementing said second counter when said second enable signal is present, and said first increment signal and said second increment signal respectively incrementing said first and second counters concurrently in response to a fifth predetermined instruction output signal from said memory means while said second enable signal is present.
Claim 2
Dependent Claim
404 words
A data processing system comprising: memory means having an input and an output, said memory means providing a first series of instruction output signals in response to first address select signals applied to the input of said memory means and a second series of instruction output signals in response to second address select signals applied to the input of said memory means; first counter means coupled to said memory means and producing said first address select signals to be applied to the input of said memory means; second counter means coupled to said memory means and producing said second address select signals to be applied to the input of said memory means; enabling means interposed between the output of said memory means and a first input of each of said first and second counter means in coupled relationship therewith for producing one of either a first enable signal to said first counter means in response to a first predetermined instruction output signal from said memory means or a second enable signal to said second counter means in response to a second predetermined instruction output signal from said memory means; said first enable signal allowing said first counter means to produce said first address select signals applied to the input of said memory means to produce said first series of instruction output signals from said memory means, and said second enable signal allowing said second counter means to produce said second address select signals applied to the input of said memory means to produce said second series of instruction output signals from said memory means; and incrementing means coupled between the output of said memory means and a second input of each of said first and second counter means for producing a first increment signal to said first counter means in response to a third predetermined instruction output signal from said memory means or a second increment signal to said second counter means in response to a fourth predetermined instruction output signal from said memory means; said first increment signal incrementing said first counter when said first enable signal is present and said second increment signal incrementing said second counter when said second enable signal is present, and said first increment signal and said second increment signal respectively incrementing said first and second counters concurrently in response to a fifth predetermined instruction output signal from said memory means while said second enable signal is present.
Claim 3
Dependent Claim
27 words
The system as in claim 1 wherein said first counter means is incremented a predetermined number of times in response to said fifth predetermined instruction output signal.
Claim 4
Dependent Claim
19 words
The system as in claim 2 wherein said predetermined number is determined by said fifth predetermined instruction output signal.
Claim 5
Dependent Claim
33 words
The system as in claim 3 further comprising: processing means coupled to the memory means for performing arithmetic and logic operations in response to said first and second series of instruction output signals.
Claim 6
Dependent Claim
64 words
The system as in claim 4 further comprising: input means for selectively transmitting input signals to said processing means in response to input stimuli; output means coupled to said processing means for selectively providing an output representation in response to an output representation signal; and wherein said processing means includes means for selectively outputting said output representation signal in response to said input signals.
Claim 7
Dependent Claim
14 words
The system as in claim 5 wherein said data processing system is a calculator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-28 | 1990-01-27 | 1990-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-28 | 1994-01-27 | 1994-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-28 | 1998-01-27 | 1998-07-29 | $7700.00 | Window Closed / Lapsed |