Data processor system capable of providing both a computer mode and a sequencer mode of operation

Claim 1

A data processor system capable of providing both a computer mode and a sequencer mode of operation comprising; a processor unit including a main memory unit for storing data, a train of computer mode instructions and a train of sequencer mode instructions, including mode change instructions; a controlling unit for sequentially reading out the instructions in said main memory unit and for outputting a series of controlling signals for use in executing said instructions; and a data section responsive to said controlling signals from said controlling unit for performing computer mode and sequencer mode operations; and a plurality of input-output units connected with said processor unit for sending and receiving data between an external apparatus and said processor unit; said controlling unit including; an instruction register composed of an instruction code part and an address part for retaining an instruction having an instruction code portion and an address portion read out from said main memory; a first controlling section operated only in response to computer mode instructions and including, a first instruction decoder connected to said instruction code part of said instruction register through a first selecting gate opened when said computer mode instructions are to be executed, for generating a selecting signal in response to the instruction code portion of said computer mode instruction retained by said instruction register; a plurality of instruction control modules each of which generates controlling signals for use in executing a computer mode instruction when selected by said selecting signal of said first instruction decoder; and a first mode change module responsive to the selecting signal of said first instruction decoder for generating a signal for opening a second selecting gate connected to the instruction code part of said instruction register in response to a first mode change instruction in said instruction register instructing that the mode of operation of the system is to be changed from the computer mode to the sequencer mode; a second controlling section operated only in response to a sequencer mode instruction, including a second instruction decoder connected to said instruction code part of said instruction register through said second selecting gate which is opened when said sequencer mode instructions are to be executed, for generating a selecting signal in response to the instruction code portion of said sequencer mode instruction retained by said instruction register; a plurality of instruction control modules each of which generates controlling signals for use in executing a sequencer mode instruction when selected by said selecting signal of said second instruction decoder; and a second mode change module responsive to the selecting signal of said second instruction decoder for generating a signal for opening said first selecting gate in response to a second mode change instruction in said instruction register instructing that the mode of operation of the system is to be changed from the sequencer mode to the computer mode; and said data section including arithmetic logic means responsive to the controlling signals from said controlling unit and data from said input-output units for controlling an input-output unit designated by the address portion of an instruction word.