Apparatus for direct data transfer among central processing units

Claim 1

Apparatus for accomplishing data transfer between first and second central processor means comprising: memory means for storing a command table and an interrupt table, said command table including a storage location for a first command, said first command comprising a command to said second central processor means to transfer selected digital data to said first central processor means; said first central processor means being operative to write said first command into said storage location in said memory means and to subsequently write a first digital code to a location in said interrupt table, said code indicating interruption of said second central processor means; decoder means responsive to writing of said first digital code into said memory means to generate a first interrupt to said second central processor means prior to data transfer to said second processor means; first, second and third buffer means, said first and second buffer means having respective first and second outputs connected for transferring data to and from said first central processor means, said third buffer means having a third output connected for transferring data to and from said second processor means, said second and third buffer means having their respective outputs connected for data transfer over a common bus means, the bus means providing for direct data transfer without intermediate storage between said second and third buffer means; said second central processor means being responsive to said first interrupt to read said first command from said memory means and to transfer said selected digital data over said bus means through said second and third buffer means to said first central processor means in response to said first command; wherein said first command and first digital code are written to said memory means through said first buffer means by said first central processor means.