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US4602374A
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Multi-level decision circuit
Assignee: NTT Inc
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Filing: 1985-02-19
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Granted: 1986-07-22
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Expires: 2005-02-19
Abstract
Abstract An input multi-level amplitude signal of 2 M levels is supplied via a DC level controller to an AD converter for conversion into an N-bit (N being an integer greater than M) digital signal, and M high-order bits of the digital signal are provided as decided outputs. It is decided by a decision means whether a deviation of the DC level of the multi-level amplitude signal at the input side of the AD converter is in excess of a predetermined value. When the deviation of the DC level is decided less than the predetermined value, the outputs of bits less significant than the Mth bit in the digital signal are integrated for input as a DC level control signal into the DC level controller, correcting the deviation of the DC level. When it is decided by the decision means that the deviation of the DC level is greater than the predetermined value, at least one of the M high-order bit outputs in the output digital signal is integrated for input as a DC level control signal into the DC level controller, correcting the deviation of the DC level.
Inventors
- 👤 Yasuhisa Nakamura
- 👤 Yoichi Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:29
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/02; H04L27/06; H04L25/00; H04L25/02; H04L25/06; H04L25/061; H04L25/066; H04L25/067
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
196 words
A multi-level signal decision circuit comprising: a DC level control means supplied with a multi-level amplitude signal of 2 M (M being an integer equal to or greater than 2) levels, for changing, by a DC level control signal, the DC level to be superimposed on the output multi-level amplitude signal; an AD converter connected to the output side of said DC level control means, for converting its output multi-level amplitude signal into a digital signal of N (N being an integer greater than M) bits and providing its M high-order bits as a multi-level decided output to an output terminal; a feedback signal generating means supplied with the output of at least an (M+1)th one of (M+1)th and less significant bits of the AD converter output and at least one of its M high-order bits, for generating a DC level control feedback signal; and a low-pass filter for integrating the DC level control feedback signal from said feedback signal generating means and feeding it as the DC level control signal back to said DC level control means, each of said feedback signal generating means and said low-pass filter constituting a part of a feedback system.
Claim 2
Dependent Claim
196 words
A multi-level signal decision circuit comprising: a DC level control means supplied with a multi-level amplitude signal of 2 M (M being an integer equal to or greater than 2) levels, for changing, by a DC level control signal, the DC level to be superimposed on the output multi-level amplitude signal; an AD converter connected to the output side of said DC level control means, for converting its output multi-level amplitude signal into a digital signal of N (N being an integer greater than M) bits and providing its M high-order bits as a multi-level decided output to an output terminal; a feedback signal generating means supplied with the output of at least an (M+1)th one of (M+1)th and less significant bits of the AD converter output and at least one of its M high-order bits, for generating a DC level control feedback signal; and a low-pass filter for integrating the DC level control feedback signal from said feedback signal generating means and feeding it as the DC level control signal back to said DC level control means, each of said feedback signal generating means and said low-pass filter constituting a part of a feedback system.
Claim 3
Dependent Claim
135 words
A multi-level decision circuit according to claim 1 which comprises a decision means for deciding whether a deviation of the DC level superimposed on the multi-level amplitude signal at the input side of the AD converter is greater or smaller than a predetermined value, and wherein said feedback signal generating means includes switch means for providing, in response to an output decision signal from said decision means, the said at least (M+1)th bit output as the DC level control feedback signal when it is decided that the deviation of the DC level is less than the predetermined value, and providing the said at least one of the M high-order bits as the DC level control feedback signal only when it is decided that the deviation of the DC level is greater than the predetermined value.
Claim 4
Dependent Claim
99 words
A multi-level decision circuit according to claim 2 wherein said decision means decides whether said feedback system is in a false or normal lock state, and wherein said switch means of said feedback signal generating means is a change-over switch and outputs at least one of the M high-order bit outputs as the DC level control feedback signal when it is decided that said feedback system is in the false lock state, and outputs only the (M+1)th bit output as the DC level feedback signal when it is decided that said feedback system is in the normal lock state.
Claim 5
Dependent Claim
102 words
A multi-level decision circuit according to claim 2 wherein said decision means decides whether said feedback system is in a false or normal lock state, wherein said switch means of said feedback signal generating means is an ON-OFF switch, wherein the (M+1)th bit output is always provided as the DC level control feedback signal, and wherein when it is decided that said feedback system is in the false lock state, said ON-OFF switch is turned ON and at least one of the M high-order bit outputs is superimposed on the (M+1)th bit output for output as the DC level control feedback signal.
Claim 6
Dependent Claim
56 words
A multi-level decision circuit according to claim 3 or 4 wherein said decision means decides whether the deviation of the DC level exceeds the predetermined value depending on a ratio of the probabilities of occurrence of a "1" and "0" with respect to at least one of the M high-order bit outputs of said AD converter.
Claim 7
Dependent Claim
48 words
A multi-level decision circuit according to claim 3 or 4 wherein said decision means decides whether the deviation of the DC level exceeds the predetermined value depending upon whether an average voltage of the most significant bit output of said AD converter is higher than a predetermined value.
Claim 8
Dependent Claim
56 words
A multi-level decision circuit according to claim 3 or 4 wherein said decision means branches the input multi-level amplitude signal of said AD converter, integrates the branched output and decides whether the deviation of the DC level exceeds the predetermined value depending upon whether the level of the integrated output is higher than a predetermined value.
Claim 9
Dependent Claim
111 words
A multi-level decision circuit according to claim 2 wherein said decision means decides whether said feedback system is likely to be in a false lock state or is in a normal lock state, and wherein the number N of bits of the output digital signal of said AD converter is two or more larger than the said M and said decision means decides whether the absolute value of the N-bit digital output of said AD converter is larger than a predetermined value smaller than a minimum signal level interval of the input multi-level amplitude signal, thereby deciding whether the deviation of the DC level is in excess of the predetermined value.
Claim 10
Dependent Claim
91 words
A multi-level decision circuit according to claim 8 wherein said switch means is a change-over switch and outputs only the (M+1)th bit output as the DC level control feedback signal when it is decided by said decision means that the deviation of the DC level is less than the predetermined value and, outputs only at least one of the M high-order bit outputs as the DC level control feedback signal when it is decided by said decision means that the deviation of the DC level is greater than the predetermined value.
Claim 11
Dependent Claim
101 words
A multi-level decision circuit according to claim 8 wherein said switch means is an ON-OFF switch, wherein the (M+1)th and less significant bit outputs in the output digital signal of said AD converter are always provided as the DC level control feedback signal, and wherein when it is decided by said decision means that the deviation of the DC level is greater than the predetermined value, said ON-OFF switch is turned ON and at least one of the M high-order bit outputs is superimposed on the (M+1)th and less significant bit outputs for output as the DC level control feedback signal.
Claim 12
Dependent Claim
95 words
A multi-level decision circuit according to claim 1, 2, 3 or 4, wherein the number N of bits of the output digital signal from said AD converter is two or more larger than the said M, and wherein said feedback signal generating means comprises a DA converter for converting the (M+1)th and less significant bit outputs in the output digital signal into an analog signal for output as the DC level control feedback signal when it is decided by said decision means that the deviation of the DC level is less than the predetermined value.
Claim 13
Dependent Claim
69 words
A multi-level decision circuit according to claim 8, 9 or 10, wherein said feedback signal generating means comprises a DA converter for converting the (M+1)th and less significant bit outputs in the output digital signal into an analog signal for output as the DC level control feedback signal when it is decided by said decision means that the deviation of the DC level is less than the predetermined value.
Claim 14
Dependent Claim
71 words
A multi-level decision circuit according to claim 2 wherein the decision means comprises a first means for deciding whether a feedback system is likely to be in a false lock state or is in a normal lock state, a second means for deciding whether the feedback system is in the false lock state or normal lock state, and an OR circuit for ORing the outputs of the first and second means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |