Microcomputer addressing system and electronic timepiece utilizing the same

Claim 2

A memory addressing system for a microcomputer, comprising: instruction data generating means for generating instruction data for designating operations of said microcomputer, including; read only memory means having outputs for storing a program, and instruction register means coupled to said read only memory means outputs for storing instruction data obtained from said read only memory means and providing said instruction data, said instruction data having a plurality of bits; control means coupled to said instruction data generating means for executing said operations designated by said instruction data; said control means comprising change signal generating means said change signal generating means including; detecting gate means having an output, said detecting gate means being coupled to said instruction register means and responsive to said plurality of bits of said instruction data for providing a signal indicative thereof at said detecting gate means output when predetermined instruction data is received from said instruction data generating means; logical state storing means coupled to said change signal generating means for storing a first logical state or a second logical state when said change signal is generated; storage means having a multiplicity of one-bit memory cells connected to address signals for designating addresses, wherein a plurality of memory cells out of said multiplicity of memory cells are designated as one set by one of said address signals; and address decoder means coupled to said instruction data generating means and said storage means for receiving address data included in said instruction data for instructing reading or writing of the data from or to said storage means and for providing said address signal to said storage means; said address decoder means including logic means for generating a plurality of said address signals for one of said address data for selectively providing one of said plurality of address signals in accordance with the output from said logical state storing means and said logic means comprises a pair of logic gate means controlled responsive to the output signal from said logical state storing means, whereby one of said logic gate means is enabled to provide said address signal, wherein: said logical state storing means comprises flip-flop means, having an output, for storing said first logical state or said second logical state; and inverter means, having an output, said inverter means being coupled to said output of said flip-flop means for inverting the polarity of a signal received therefrom and for providing said inverted signal at said output; said output of said flip-flop means being coupled to one of said pair of logic gate means of said address decoder means and said output of said inverter being coupled to the other logic gate means.

Claim 3

A memory addressing system for a microcomputer, comprising: instruction data generating means for generating instruction data for designating operations of said microcomputer, including; read only memory means having outputs for storing a program, and instruction register means coupled to said read only memory means outputs for storing instruction data obtained from said read only memory means and providing said instruction data, said instruction data having a plurality of bits; control means coupled to said instruction data generating means for executing said operations designated by said instruction data; said control means comprising change signal generating means said change signal generating means including; detecting gate means having an output, said detecting gate means being coupled to said instruction register means and responsive to said plurality of bits of said instruction data for providing a signal indicative thereof at said detecting gate means output when predetermined instruction data is received from said instruction data generating means; and a plurality of logic gate means having said output of said detecting gate means coupled thereto and one bit of said instruction data coupled thereto, the outputs of said plurality of logic gate means constituting a plurality of change signals; logical state storing means coupled to said change signal generating means for storing a first logical state or a second logical state when said change signal is generated comprising a plurality of flip-flops having an output for receiving said plurality of change signals, and a plurality of said inverters coupled to the outputs of said flip-flops; storage means having a multiplicity of one-bit memory cells connected to address signals for designating addresses, wherein a plurality of memory cells out of said multiplicity of memory cells are designated as one set by one of said address signals; and address decoder means coupled to said instruction data generating means and said storage means for receiving address data included in said instruction data for instructing reading or writing of the data from or to said storage means and for providing said address signal to said storage means; said address decoder means comprising logic gate means coupled to said output of said flip-flops and logic means for generating a plurality of said address signals for one of said address data for selectively providing one of said plurality of address signals in accordance with the output from said logical state storing means and said logic means comprises a plurality of pairs of logic gate means coupled to receive output signals from said inverters and controlled responsive to the output signal from said logical state storing means, whereby one of said logic gate means is enabled to provide said address signal.

Claim 4

A memory addressing system for a microcomputer, comprising: instruction data generating means for generating instruction data for designating operations of said microcomputer, including; read only memory means having outputs for storing a program, and instruction register means coupled to said read only memory means outputs for storing instruction data obtained from said read only memory means and providing said instruction data, said instruction data having a plurality of bits; control means coupled to said instruction data generating means for executing said operations designated by said instruction data; said control means comprising change signal generating means said change signal generating means including; detecting gate means having an output, said detecting gate means being coupled to said instruction register means and responsive to said plurality of bits of said instruction data for providing a signal indicative thereof at said detecting gate means output when predetermined instruction data is received from said instruction data generating means; and a plurality of logic gate means having said output of said detecting gate means coupled thereto and one bit of said instruction data coupled thereto, the outputs of said plurality of logic gate means constituting a plurality of change signals; logical state storing means coupled to said change signal generating means for storing a first logical state or a second logical state when said change signal is generated comprising a plurality of flip-flops having an output for receiving said plurality of change signals, and a plurality of said inverters coupled to the outputs of said flip-flops; storage means having a multiplicity of one-bit memory cells connected to address signals for designating addresses, wherein a plurality of memory cells out of said multiplicity of memory cells are designated as one set by one of said address signals; and address decoder means coupled to said instruction data generating means and said storage means for receiving address data included in said instruction data for instructing reading or writing of the data from or to said storage means and for providing said address signal to said storage means; said address decoder means comprising logic gate means coupled to said output of said flip-flops and logic means for generating a plurality of said address signals for one of said address data for selectively providing one of said plurality of address signals in accordance with the output from said logical state storing means and said logic means comprises a plurality of pairs of logic gate means coupled to receive output signals from said inverters and controlled responsive to the output signal from said logical state storing means, whereby one of said logic gate means is enabled to provide said address signal.

Claim 5

An electronic timepiece employing a microcomputer, comprising: clock generator means for generating various clock signals; instruction data generating means for generating instruction data having a plurality of bits for designating various operations said instruction data generating means including: read only memory means having outputs for fixedly storing a program, said program being readable from said outputs and instruction register means coupled to said outputs of said read only memory means, for storing instruction data obtained from said read only memory means and for providing said instruction data having a plurality of bits; instruction bus means coupled to the outputs of said instruction data generating means for transferring said instruction data; control means coupled to said instruction bus means for executing said operations designated by said instruction data from said instruction data generating means; said control means comprising change signal generating means having detecting gate means coupled to said instruction bus means and responsive to a plurality of bits of said instruction data for detecting predetermined instruction data; logical state storing means coupled to said change signal generating means for storing a first logical state or a second logical state when said change signal is generated, comprising flip-flop means, having an output, for storing said first logical state or said second logical state; and inverter means, having an output, said inverter means being coupled to said output of said flip-flop means for inverting the polarity of a signal from said flip-flop means; storage means having a multiplicity of one-bit memory cells connected to address signals for designating addresses, wherein a plurality of memory cells out of said multiplicity of memory cells are designated as one set by one of said address signals; data bus means coupled to the inputs and outputs of said storage means for transferring data to and from said storage means; address decoder means coupled to said instruction bus means and said storage means for receiving address data included in the instruction data for instructing reading or writing of the data from or in said storage means and for providing said address signal to said storage means; said address decoder means including logic means for generating a plurality of said address signals for one said address data for selectively providing one of said plurality of address signals in accordance with the output from said logical state storing means and said logic means comprises a pair of logic gate means controlled in response to the output signal from said logical state storing means, whereby one of said pair of logic gate means is enabled to provide said address signal; said output of said flip-flop means being coupled to one of said pair of logic gate means of said address decoder and said output of said inverter being coupled to the other logic gate means. arithmetic logic means coupled to said data bus means for performing an arithmetic operation on the data from said data bus means and for providing the result thereof to said data bus means; and display means coupled to said data bus means for displaying the data obtained from said data bus.

Claim 6

An electronic timepiece employing a microcomputer, comprising: clock generator means for generating various clock signals; instruction data generating means for generating instruction data having a plurality of bits for designating various operations said instruction data generating means including: read only memory means having outputs for fixedly storing a program, said program being readable from said outputs and instruction register means coupled to said outputs of said read only memory means, for storing instruction data obtained from said read only memory means and for providing said instruction data having a plurality of bits; instruction bus means coupled to the outputs of said instruction data generating means for transferring said instruction data; control means coupled to said instruction bus means for executing said operations designated by said instruction data from said instruction data generating means; said control means comprising change signal generating means having detecting gate means coupled to said instruction bus means and responsive to a plurality of bits of said instruction data for detecting predetermined instruction data; logical state storing means coupled to said change signal generating means for storing a first logical state or a second logical state when said change signal is generated, comprising flip-flop means, having an output, for storing said first logical state or said second logical state; and inverter means, having an output, said inverter means being coupled to said output of said flip-flop means for inverting the polarity of a signal from said flip-flop means; storage means having a multiplicity of one-bit memory cells connected to address signals for designating addresses, wherein a plurality of memory cells out of said multiplicity of memory cells are designated as one set by one of said address signals; data bus means coupled to the inputs and outputs of said storage means for transferring data to and from said storage means; address decoder means coupled to said instruction bus means and said storage means for receiving address data included in the instruction data for instructing reading or writing of the data from or in said storage means and for providing said address signal to said storage means; said address decoder means including logic means for generating a plurality of said address signals for one said address data for selectively providing one of said plurality of address signals in accordance with the output from said logical state storing means and said logic means comprises a pair of logic gate means controlled in response to the output signal from said logical state storing means, whereby one of said pair of logic gate means is enabled to provide said address signal; said output of said flip-flop means being coupled to one of said pair of logic gate means of said address decoder and said output of said inverter being coupled to the other logic gate means. arithmetic logic means coupled to said data bus means for performing an arithmetic operation on the data from said data bus means and for providing the result thereof to said data bus means; and display means coupled to said data bus means for displaying the data obtained from said data bus.

Claim 7

An electronic timepiece employing a microcomputer, comprising: clock generator means for generating various clock signals; instruction data generating means for generating instruction data having a plurality of bits for designating various operations said instruction data generating means including: read only memory means having outputs for fixedly storing a program, said program being readable from said outputs and instruction register means coupled to said outputs of said read only memory means, for storing instruction data obtained from said read only memory means and for providing said instruction data having a plurality of bits; instruction bus means coupled to the outputs of said instruction data generating means for transferring said instruction data; control means coupled to said instruction bus means for executing said operations designated by said instruction data from said instruction data generating means; said control means comprising change signal generating means, comprising detecting gate means coupled to said instruction bus means and responsive to a plurality of bits of said instruction data for detecting predetermined instruction data; and a plurality of logic gate means having the output of said detecting gate means coupled thereto and one-bit of said instruction bus coupled thereto, the outputs of said plurality of logic gate means constituting a plurality of change signals; logical state storing means coupled to said change signal generating means for storing a first logical state or a second logical state when said change signal is generated, comprising a plurality of said flip-flops receiving said plurality of change signals, and a plurality of said inverters coupled to the outputs of said flip-flops; storage means having a multiplicity of one-bit memory cells connected to address signals for designating addresses, wherein a plurality of memory cells out of said multiplicity of memory cells are designated as one set by one of said address signals; data bus means coupled to the inputs and outputs of said storage means for transferring data to and from said storage means; address decoder means coupled to said instruction bus means and said storage means for receiving address data included in the instruction data for instructing reading or writing of the data from or in said storage means and for providing said address signal to said storage means; said decoder means including: logic means for generating a plurality of said address signals for one said address for selectively providing one of said plurality of address signals in accordance with the output from said logical state storing means and said logic means comprises a pair of logic gate means controlled in response to the output signal from said logical state storing means, whereby one of said pair of logic gate means is enabled to provide said address signal; said logical gate means being coupled to said outputs of said flip-flops, and a plurality of pairs of said logic gate means receiving the outputs of said inverters; arithmetic logic means coupled to said data bus means for performing an arithmetic operation on the data from said data bus means and for providing the result thereof to said data bus means; and display means coupled to said data bus means for displaying the data obtained from said data bus.

Claim 8

An electronic timepiece employing a microcomputer, comprising: clock generator means for generating various clock signals; instruction data generating means for generating instruction data having a plurality of bits for designating various operations said instruction data generating means including: read only memory means having outputs for fixedly storing a program, said program being readable from said outputs and instruction register means coupled to said outputs of said read only memory means, for storing instruction data obtained from said read only memory means and for providing said instruction data having a plurality of bits; instruction bus means coupled to the outputs of said instruction data generating means for transferring said instruction data; control means coupled to said instruction bus means for executing said operations designated by said instruction data from said instruction data generating means; said control means comprising change signal generating means, comprising detecting gate means coupled to said instruction bus means and responsive to a plurality of bits of said instruction data for detecting predetermined instruction data; and a plurality of logic gate means having the output of said detecting gate means coupled thereto and one-bit of said instruction bus coupled thereto, the outputs of said plurality of logic gate means constituting a plurality of change signals; logical state storing means coupled to said change signal generating means for storing a first logical state or a second logical state when said change signal is generated, comprising a plurality of said flip-flops receiving said plurality of change signals, and a plurality of said inverters coupled to the outputs of said flip-flops; storage means having a multiplicity of one-bit memory cells connected to address signals for designating addresses, wherein a plurality of memory cells out of said multiplicity of memory cells are designated as one set by one of said address signals; data bus means coupled to the inputs and outputs of said storage means for transferring data to and from said storage means; address decoder means coupled to said instruction bus means and said storage means for receiving address data included in the instruction data for instructing reading or writing of the data from or in said storage means and for providing said address signal to said storage means; said decoder means including: logic means for generating a plurality of said address signals for one said address for selectively providing one of said plurality of address signals in accordance with the output from said logical state storing means and said logic means comprises a pair of logic gate means controlled in response to the output signal from said logical state storing means, whereby one of said pair of logic gate means is enabled to provide said address signal; said logical gate means being coupled to said outputs of said flip-flops, and a plurality of pairs of said logic gate means receiving the outputs of said inverters; arithmetic logic means coupled to said data bus means for performing an arithmetic operation on the data from said data bus means and for providing the result thereof to said data bus means; and display means coupled to said data bus means for displaying the data obtained from said data bus.