US4475176A
Expired / Lapsed
US
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Memory control system
Assignee: Toshiba Corp
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Filing: 1982-07-27
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Granted: 1984-10-02
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Expires: 2002-07-27
Abstract
Abstract A memory multiplex address system which increases the effective size of the address space of a processor. A first memory from which data is normally read and a second memory into which data is normally written are assigned the same address space. A read/write signal is employed to select the appropriate memory. In a second mode, data may be written into the first memory and read from the second memory. Alternatively, any conceivable address space layout may be employed in the second mode.
Inventors
- 👤 Takatoshi Ishii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:50
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
66 words
A memory multiplex addressing system comprising: a first memory; a second memory; means for addressing said first and second memories, each address corresponding to one location in each of said first and second memories; and means for selecting one of said first and second memories when data is to be read and the other of said first and second memories when data is to be written.
Claim 2
Dependent Claim
66 words
A memory multiplex addressing system comprising: a first memory; a second memory; means for addressing said first and second memories, each address corresponding to one location in each of said first and second memories; and means for selecting one of said first and second memories when data is to be read and the other of said first and second memories when data is to be written.
Claim 3
Dependent Claim
92 words
A memory multiplex addressing system as recited in claim 1, wherein: said first and second memories are both read/write memories; said selecting means includes means for selecting: (1) said first memory when data is to be read and said second memory when data is to be written during a first mode, and (2) said first memory when data is to be written and said second memory when data is to be read during a second mode; and said system further comprises means for instituting either one of said first and second modes.
Claim 4
Dependent Claim
84 words
A memory multiplex addressing system as recited in claim 1 wherein: said second memory is a read/write memory; and said selecting means includes means for selecting: (1) said first memory when data is to be read and said second memory when data is to be written during a first mode, and (2) said second memory when data is to be either read or written during a second mode; and said system further comprises means for instituting either one of said first and second modes.
Claim 5
Dependent Claim
134 words
A memory multiplex addressing system as recited in claim 1 wherein: said system further comprises a third memory; said selecting means includes means for selecting: (1) said third memory in response to a third memory address signal, one of said first and second memories in response to both a first and second memory address signal and a read signal, and the other of said first and second memories in response to both said first and second memory address signal and a write signal during a first mode, and (2) said first memory in response to said first and second memory address signal, and said second memory in response to said third memory address signal during a second mode; and said system further comprises means for instituting either one of said first and second modes.
Claim 6
Dependent Claim
121 words
A memory multiplex addressing system as recited in claim 1 wherein: said system further comprises a third memory; said selecting means includes means for selecting one of said first and second memories in response to a first and second memory address signal and a read signal, the other of said first and second memories in response to both said first and second memory address signal and a write signal, and for selecting (1) said third memory in response to a third memory address signal during a first mode, and (2) said second memory in response to said third memory address signal during a second mode; and said system further comprises means for instituting either one of said first and second modes.
Claim 7
Dependent Claim
135 words
A memory multiplex addressing system as recited in claim 1 wherein: said second memory is a read/write memory; said system further comprises a third memory; said selecting means includes means for selecting said first memory in response to a first and second memory address signal and a read signal, and said second memory in response to said first and second memory address signal and a write signal, and for selecting (1) said third memory in response to a third memory address signal during a first mode, and (2) said third memory in response to said third memory address signal and a write signal, and said second memory in response to said third memory address signal and a read signal; and said system further comprises means for instituting either one of said first and second modes.
Claim 8
Dependent Claim
21 words
A memory multiplex addressing system as recited in claim 1, 4 or 5 wherein said second memory is a read/write memory.
Claim 9
Dependent Claim
19 words
A memory multiplex addressing system as recited in claim 7, wherein said second memory comprises a CRT refresh memory.
Claim 10
Dependent Claim
79 words
A memory multiplex addressing system as recited in claim 2, 3, 4 or 6, wherein said means for selecting and means for instituting comprise: decoding means for selecting both said first and said second memories; a flip-flop for generating a mode setting signal representing a selected mode; and selecting means, responsive to said flip-flop and said decoding means, for selecting either one of said first and second memories in response to said mode setting signal and a read/write signal.
Claim 11
Dependent Claim
24 words
A memory multiplex addressing system as recited in claim 1, 3, 4, 5 or 6, wherein said first memory is a read only memory.
Claim 12
Dependent Claim
21 words
A memory multiplex addressing system as recited in claim 4, 5 or 6, wherein said third memory is a read/write memory.
References Cited (Backward Citations)
US4206476A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-02 | 1988-04-02 | 1988-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-02 | 1992-04-02 | 1992-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-02 | 1996-04-02 | 1996-10-02 | $7700.00 | Window Closed / Lapsed |