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Patent US4601781A successfully refreshed from Google Patents.
US4601781A
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Method for improving step coverage of dielectrics in VLSI circuits
Assignee: Nortel Networks Ltd
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Filing: 1984-10-09
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Granted: 1986-07-22
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Expires: 2004-10-09
Abstract
Abstract Particularly for use in multilevel metallization structures in which the underlying topography consists of fine and sharply contoured conductor lines produced by dry etching, conformal or near planar dielectric coatings are produced by depositing a dielectric layer to a thickness over the conductor of at least three times the conductor thickness. The dielectric is then anisotropically etched back to a thickness comparable with that of the underlying conductor. By this method a smooth dielectric top surface can be obtained without the requirement for multiple processing steps characterizing alternative planarizing techniques.
Inventors
- 👤 Jacques S. Mercier
- 👤 Vu Q. Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:26
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
91 words
In a process for making VLSI circuits, a method of depositing a dielectric layer over sharply profiled conducting regions spaced from one another and formed on a substrate, the method comprising depositing a dielectric layer over the wafer to a thickness appreciably greater than the thickness of the conducting regions until differential growth caused by the sharp profiles of the conducting regions ceases, and then etching the dielectric layer over the wafer until the dielectric layer has a thickness over the conducting regions comparable with the thickness of the conducting regions.
Claim 2
Dependent Claim
91 words
In a process for making VLSI circuits, a method of depositing a dielectric layer over sharply profiled conducting regions spaced from one another and formed on a substrate, the method comprising depositing a dielectric layer over the wafer to a thickness appreciably greater than the thickness of the conducting regions until differential growth caused by the sharp profiles of the conducting regions ceases, and then etching the dielectric layer over the wafer until the dielectric layer has a thickness over the conducting regions comparable with the thickness of the conducting regions.
Claim 3
Dependent Claim
20 words
A method as claimed in claim 1, in which the dielectric layer is deposited by low pressure chemical vapour deposition.
Claim 4
Dependent Claim
17 words
A method as claimed in claim 1, in which the dielectric layer is deposited by plasma deposition.
Claim 5
Dependent Claim
19 words
A method as claimed in claim 2, in which the dielectric layer is removed by an anisotropic etching technique.
Claim 6
Dependent Claim
18 words
A method as claimed in claim 4 in which the dielectric layer is etched by reactive ion etching.
Claim 7
Dependent Claim
17 words
A method as claimed in claim 4 in which the dielectric layer is etched by plasma etching.
Claim 8
Dependent Claim
24 words
A method as claimed in claim 1 in which the dielectric layer is deposited to at least twice the thickness of the conducting regions.
Claim 9
Dependent Claim
24 words
A method as claimed in claim 1 in which the dielectric layer is deposited to approximately three times the thickness of the conducting regions.
Claim 10
Dependent Claim
20 words
A method as claimed in claim 1 further comprising depositing and patterning a conducting layer over the etched dielectric layer.
Claim 11
Dependent Claim
34 words
A method as claimed in claim 1 in which the metallization is one of the group consisting of aluminum, polysilicon, an alloy of aluminum and silicon, a refractory metal and a refractory metal silicide.
Claim 12
Dependent Claim
23 words
A method as claimed in claim 1 in which the dielectric is one of the group consisting of doped and undoped silicate glass.
References Cited (Backward Citations)
US4377438A
Cited
US4524508A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |