Data processing system

Claim 2

A data processing system, comprising: measurement information storing means for storing measurement information corresponding to performance measurement items; measurement control information storing means for storing performance measurement item information and performance measurement condition information; a timer; storage control means for controlling information storage in said measurement control information storing means and loading an interval in said timer; and performance measurement processing means which is started by an interrupt generated by said timer after the interval loaded by said storage control means has expired and for collecting measurement information and storing same in said measurement information storing means based on said performance measurement item information and performance measurement condition information.

Claim 3

A data processing system according to claim 1, further comprising performance measurement setting instructions, and said storage control means is started by an interrupt caused by said instructions.

Claim 4

A data processing system according to claim 2, wherein said performance measurement condition information comprises sampling period information to be loaded into said timer by said storage control means.

Claim 5

A data processing system according to claims 1, 2 or 3, wherein said system further comprises main storage having a firmware domain storing instruction groups, and processing by said storage control means and said performance measurement processing means is executed by the instruction groups provided in the firmware domain of said main storage.

Claim 6

A data processing system performance measurement process using instructions having an invalid operation code in the data processing system which includes an interrupt timer, comprising the steps of: (a) detecting an interrupt caused by one of the instructions with an invalid op code; (b) setting measurement parameters and enabling an analysis mode, and starting the performance measurement by loading the interrupt timer with an analysis interrupt interval; (c) detecting an interrupt by the interrupt timer; (d) collecting performance measurement data, updating a performance log and re-loading the interrupt timer with the analysis interrupt interval; (e) performing steps (c) and (d) a plurality of times; and (f) detecting an interrupt by one of the instructions with an invalid op code, stopping the performance measurement and resetting the analysis mode to disable.

Claim 7

A data processing system performance measurement process using instructions having an invalid operation code in the data processing system which includes an interrupt timer, comprising the steps of: (a) detecting an interrupt caused by one of the instructions with an invalid op code; (b) setting measurement parameters and enabling an analysis mode, and starting the performance measurement by loading the interrupt timer with an analysis interrupt interval; (c) detecting an interrupt by the interrupt timer; (d) collecting performance measurement data, updating a performance log and re-loading the interrupt timer with the analysis interrupt interval; (e) performing steps (c) and (d) a plurality of times; and (f) detecting an interrupt by one of the instructions with an invalid op code, stopping the performance measurement and resetting the analysis mode to disable.

Claim 8

A process according to claim 5, wherein step (a) comprises the steps of: (ai) determining whether the interrupt is by one of the instructions; and (aii) decoding the invalid operation code.

Claim 9

A process according to claim 5, wherein the instructions include a mode set instruction, a start instruction, and said step (b) comprises the steps of: (bi) setting the measurement parameters and enabling the analysis mode; and (bii) starting the performance measurement if the instruction is a start instruction.

Claim 10

A process according to claim 7, wherein the measurement process has enable and disable states, and step (bi) comprises the steps of: (1) setting a condition code to a first value if the process is not in the disable state; (2) changing the state from disable to enable if the process is in the disable state; (3) initializing the performance log if the process state has been changed in step (2); (4) loading the measurement parameters into a measurement control table if the process has been changed in step (2); (5) setting a sampling interval control bit if the process has been changed in step (2); and (6) setting the condition code to a second value if the process has been changed in step (2).

Claim 11

A process according to claim 7, wherein the measurement process includes enable, disable, start and stop states and a sampling interval control bit, and step (bii) comprises the steps of: (1) setting a condition code to a first value if the process is in the start state; (2) setting the condition code to a second value if the process is in the disable state and not in the start state; (3) changing the state from stop to start if the process is not in the start state and not in the disable state; (4) loading the interrupt timer with a first value if the sampling interval control bit is set and if the state has been changed in step (3); (5) loading the interrupt timer with a second value if the sampling interval control bit is not set and if the state has been changed in step (3); (6) turning on an interrupt mask if the state has been changed in step (3); and (7) setting the condition code to a third value if the state has been changed in step (3).

Claim 12

A process according to claim 7, wherein the measurement process includes start and stop states, and step (biii) comprises the steps of: (1) setting a condition code to a first value if the process is not in the start state; (2) changing the state from start to stop if the process is in the start state; (3) turning off an interrupt mask if the state has been changed in step (2); and (4) setting the condition code to a second value if the state has been changed in step (2).

Claim 13

A process according to claim 7, wherein the measurement process includes start, disable and enable states, and step (biv) comprises the steps of: (1) setting a condition code to a first value if the process is in the start state; (2) setting the condition code to a second value if the process is not in the start state and in the disable state; (3) changing the state from enable to disable if the process is not in the start state and not in the disable state; and (4) setting the condition code to a third value if the state has been changed in step (3).

Claim 14

A process according to claim 5, wherein step (d) comprises the steps of: (di) turning on an internal flag; (dii) fetching a log area address and decoding a performance measurement identifier; (diii) collecting performance measurement data corresponding to the identifier and updating the performance log; (div) loading the interrupt timer with the interrupt interval; and (dv) turning off the internal flag.

Claim 15

A process according to claim 5, wherein the instructions include a stop instruction and a mode reset instruction, and said step (f) comprises the steps of: (fi) stopping the performance measurement if the instruction is the stop instruction; and (fii) setting the analysis to disable if the instruction is the mode instruction.

Claim 16

A data processing system performance measuring system using instructions having invalid operation codes, comprising: storage means for storing an operating system program in an operating system storage area and a measurement system program in a measurement system program storage area; and a central processing unit connected to said storage means and comprising: an instruction register; a control storage connected to said instruction register and storing micro-operation words each having an invalidity indicator and corresponding to the invalid operation codes; a control storage data register connected to said control storage and generating a first interrupt signal when the invalidity indicator is present; a timer for generating a second interrupt signal; an interrupt control circuit, connected to said control data storage register and said timer, for outputting the address of the operating system storage area; an address register, connected to said interrupt control circuit and said storage means, for receiving the output from said interrupt control circuit and addrressing said storage means; and address modifying means, connected to said control storage data register and said timer, for modifying the address in said address register to address the measurement system program area in dependence upon the first and second interrupt signals.

Claim 17

A data processing system performance measuring system using instructions having invalid operation codes, comprising: storage means for storing an operating system program in an operating system storage area and a measurement system program in a measurement system program storage area; and a central processing unit connected to said storage means and comprising: an instruction register; a control storage connected to said instruction register and storing micro-operation words each having an invalidity indicator and corresponding to the invalid operation codes; a control storage data register connected to said control storage and generating a first interrupt signal when the invalidity indicator is present; a timer for generating a second interrupt signal; an interrupt control circuit, connected to said control data storage register and said timer, for outputting the address of the operating system storage area; an address register, connected to said interrupt control circuit and said storage means, for receiving the output from said interrupt control circuit and addrressing said storage means; and address modifying means, connected to said control storage data register and said timer, for modifying the address in said address register to address the measurement system program area in dependence upon the first and second interrupt signals.

Claim 18

A system according to claim 14, wherein said data processing system generates a third interrupt signal and said address modifying means comprises: a system control latch connected to said control storage data register and said timer and receiving the third interrupt signal; a system base register; and a control gate connected to said system control latch, said system base register and said address register.