US4231106A
Expired / Lapsed
US
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Performance monitor apparatus and method
Assignee: Unisys Corp
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Filing: 1978-07-13
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Granted: 1980-10-28
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Expires: 1998-07-13
Abstract
Abstract Performance monitor apparatus is adapted to monitor various computer program events such as the length of time required to execute a particular program, the number of times a particular program or instruction sequence is executed during some predetermined period, etc. The apparatus includes a buffer for receiving an instruction data word from a data processor and for temporarily storing the data word, a register having a plurality of bistable elements each of which is adapted to produce either a first or second output signal in response to receipt of a first or second operation signal respectively and receipt of a select signal, a select logic circuit for applying a select signal to a particular bistable element identified by certain bits of the instruction data word stored in the buffer, and an operation logic circuit for supplying to the bistable elements either a first or second operation signal as determined by certain other bits of the instruction data word stored in the buffer. Each bistable element represents a different event or occurrence in a computer program being monitored and the signals produced by the bistable elements indicate the nature of the monitoring operation to be performed. The signals are supplied to timing and counting apparatus which then either measures the time over which the signals are produced or increments a count in response to receiving the signals.
Inventors
- 👤 David L. Heap
- 👤 Allen L. Kenner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3409; G06F11/3466; G06F11/348; G06F11/3419; G06F2201/00; G06F2201/86; G06F2201/88
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
136 words
Performance monitor apparatus for receiving instruction data words and for developing various output signals in response thereto, said instruction data words including address bits and operation bits, said apparatus including buffer means for receiving and temporarily registering an instruction data word, register means comprising a plurality of bistable elements, each for producing either a first or second output signal in response to receipt of a first or second operation signal respectively and receipt of a select signal, select logic means for applying a select signal to a particular bistable element identified by the address bits of the instruction data word registered in said buffer means, and means for supplying to said bistable elements either a first or second operation signal as determined by the operation bits of the instruction data word registered in said buffer means.
Claim 2
Dependent Claim
136 words
Performance monitor apparatus for receiving instruction data words and for developing various output signals in response thereto, said instruction data words including address bits and operation bits, said apparatus including buffer means for receiving and temporarily registering an instruction data word, register means comprising a plurality of bistable elements, each for producing either a first or second output signal in response to receipt of a first or second operation signal respectively and receipt of a select signal, select logic means for applying a select signal to a particular bistable element identified by the address bits of the instruction data word registered in said buffer means, and means for supplying to said bistable elements either a first or second operation signal as determined by the operation bits of the instruction data word registered in said buffer means.
Claim 3
Dependent Claim
33 words
Performance monitor apparatus as in claim 1 further comprising trigger logic means responsive to receipt of a predetermined trigger signal for enabling said buffer means to receive and register said instruction data word.
Claim 4
Dependent Claim
48 words
Performance monitor apparatus as in claim 2 wherein said trigger logic means includes manually settable switch means which may be set to represent various signal values, and means for enabling said buffer means when the value of said trigger signal matches the value set by said switch means.
Claim 5
Dependent Claim
29 words
Performance monitor apparatus as in claim 3 wherein said manually settable switch means may be set to enable said buffer means regardless of the value of said trigger signal.
Claim 6
Dependent Claim
202 words
Performance monitor apparatus as in claim 1 wherein said buffer means comprises a multiplicity of address cells and operation cells for temporarily storing the address bits and operation bits respectively of an instruction data word, wherein each of said bistable elements comprises a flip-flop having first, second and third inputs, and an output, each of said flip-flops being adapted to produce a first output signal upon receipt of both a first combination of operation signals on said first and third inputs and a select signal on said second input, and to produce a second output signal upon receipt of both a second combination of operation signals on said first and third inputs and a select signal on said second input, and wherein said select logic means comprises decoding means for decoding the address bits stored in said address cells and for applying a select signal to the second input of a particular one of said flip-flops identified by the address bits, and means for applying the contents of a first one of said operation cells to said first inputs of the flip-flops and for applying the contents of a second one of said operation cells to said third inputs of the flip-flops.
Claim 7
Dependent Claim
43 words
Performance monitor apparatus as in claim 5 wherein said select logic means further comprises logic circuitry responsive to a third one of said operation cells containing a certain bit for applying select signals to the second input of all of said bistable means.
Claim 8
Dependent Claim
40 words
Performance monitor apparatus as in claim 5 wherein each of said flip-flops comprise a JK flip-flop in which said first input is the J input, said second input is the clock input, and said third input is the K input.
Claim 9
Dependent Claim
51 words
Performance monitor apparatus as in claim 1 wherein said instruction data words include an enable bit, said apparatus further including enable logic means responsive to the storage of an enable bit in said buffer means for enabling said select logic means to apply a select signal to a selected bistable element.
Claim 10
Independent Claim
129 words
A method of monitoring events which occur in the course of executing a computer program on a data processor comprising providing monitor instructions in such computer program at predetermined locations therein, said instructions including address data and operation data, applying the address data and operation data of a monitor instruction to performance monitor apparatus for temporary storage therein when such instruction is encountered by the data processor in the course of executing the computer program, producing a certain signal specified by said operation data on one of a plurality of output terminals specified by said address data, and supplying said certain signal to timing and counting apparatus to either measure over the time said certain signal is supplied or to increment a count upon supplication of the certain signal.
Claim 11
Independent Claim
129 words
A method of monitoring events which occur in the course of executing a computer program on a data processor comprising providing monitor instructions in such computer program at predetermined locations therein, said instructions including address data and operation data, applying the address data and operation data of a monitor instruction to performance monitor apparatus for temporary storage therein when such instruction is encountered by the data processor in the course of executing the computer program, producing a certain signal specified by said operation data on one of a plurality of output terminals specified by said address data, and supplying said certain signal to timing and counting apparatus to either measure over the time said certain signal is supplied or to increment a count upon supplication of the certain signal.
Claim 12
Dependent Claim
28 words
A method as in claim 9 wherein said monitor instructions include an identifying code which is different from identifying codes of other instructions executed by the data processor.
Claim 13
Dependent Claim
53 words
A method as in claim 9 wherein said monitor instructions include at least three operation bits, two of which specify the signal to be produced in the producing step and the other of which specifies whether the signal is to be produced on all the output terminals or only on said one terminal.
Claim 14
Independent Claim
33 words
A method as in clain 9 wherein said applying step includes applying triggering signals to the performance monitor apparatus to enable temporary storage of the address data and operation data in the apparatus.
Claim 15
Independent Claim
33 words
A method as in clain 9 wherein said applying step includes applying triggering signals to the performance monitor apparatus to enable temporary storage of the address data and operation data in the apparatus.
Claim 16
Dependent Claim
43 words
A method as in claim 12 wherein said applying step further includes comparing the triggering signals with the setting of a manually settable switch, and enabling temporary storage of the address data and operation data when the triggering signals match the switch setting.
Claim 17
Dependent Claim
32 words
A method as in claim 9 wherein said producing step includes producing said certain signal on all of said output terminals when certain operation data is applied to the performance monitor register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-28 | 1984-04-28 | 1984-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-28 | 1988-04-28 | 1988-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-28 | 1992-04-28 | 1992-10-28 | $7700.00 | Window Closed / Lapsed |