Timing recovery circuit for synchronous data transmission using combination of L Bi phase and modified biphase codes

Claim 1

Timing recovery circuit for synchronous data transmission using a signal which, in the baseband, is formed by a succession of two-level signal elements, without overlap, isochronous and of duration T, able to take one of the four forms defined by the functions: ##EQU9## said circuit comprising a transition selection circuit adapted to select transitions in the received signal, in the baseband, separated from those which immediately precede them by a time-delay situated in an arbitrary range, bracketing a symbol duration of between 3/4 and 5/4 times, exclusive, the duration of a signal element, and a timebase which is synchronised on the transitions selected by said selection circuit and which delivers the signal element recovered timing, wherein said transition selection circuit comprises: a transition detector for generating a short duration pulse in response to each transition of the received signal in the base band, a gate for sorting the pulses from said transition detector, said gate being inserted between the output of said transition detector and a synchronisation input of said timebase, a first counting circuit reset to zero by the pulses generated by said transition detector and incremented by a first clock signal defining elementary time intervals which are very short relative to the duration of a signal element but longer than the duration of the pulses from said transition detector, said first counting circuit delivering a second clock signal defining elementary time intervals which are short relative to the duration of a signal element, a second counting circuit reset to zero by pulses generated by said first transition detector and incremented by the second clock signal from said first counting circuit, said second counting circuit delivering an overshoot signal when its count value is going to overshoot said given duration measured by means of pulses of said second clock signal, and a hold circuit formed by a D-type bistable having a D input receiving said overshoot signal from said second counting circuit and a clock input receiving said second clock signal from said first counting circuit, an output of said bistable controlling said gate.