US4599701A
Expired / Lapsed
US
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Complex magnitude computation
Assignee: Grumman Corp
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Filing: 1983-10-19
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Granted: 1986-07-08
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Expires: 2003-10-19
Abstract
Abstract A digital circuit is disclosed for computing the magnitude of a complex number employing piece-wise linear approximations to achieve precision without the need for iteration. An illustrative implementing circuit employs a first stage for converting the in-phase and quadrature signals to their absolute values. The resultant signals are applied to a selection circuit which selects the maximum and minimum values. The resultant signals are combined with coefficients selected as a function of the operating interval and the resultant products added to yield a signal related to the magnitude of the input complex number.
Inventors
- 👤 William M. Vojir
- 👤 Cecelia Jankowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:28
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/4806; G06F7/544; G06F7/552; G06F2207/00; G06F2207/552; G06F2207/5525
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A circuit for calculating the magnitude r of a complex number Z represented by inphase and quadrature signals A and B, respectively, comprising: (1) means for deriving signals related to the absolute values of signals A and B; (2) means for selecting the maximum (signal X) and minimum (signal Y) as between said absolute value signals; (3) means for multiplying signal X by a selected one or more of a plurality of X signal coefficients a 1 . . . a n and for multiplying signal Y by a selected one or more of a plurality of Y signal coefficients b 1 . . . b n ; (4) means responsive to said X and Y signals for selecting the operative coefficients a n , b n forming the a n X and b n Y products; and (5) means for combining said products to derive a signal relating to the magnitude r.
Claim 2
Dependent Claim
153 words
A circuit for calculating the magnitude r of a complex number Z represented by inphase and quadrature signals A and B, respectively, comprising: (1) means for deriving signals related to the absolute values of signals A and B; (2) means for selecting the maximum (signal X) and minimum (signal Y) as between said absolute value signals; (3) means for multiplying signal X by a selected one or more of a plurality of X signal coefficients a 1 . . . a n and for multiplying signal Y by a selected one or more of a plurality of Y signal coefficients b 1 . . . b n ; (4) means responsive to said X and Y signals for selecting the operative coefficients a n , b n forming the a n X and b n Y products; and (5) means for combining said products to derive a signal relating to the magnitude r.
Claim 3
Dependent Claim
57 words
The circuit as defined in claim 1 in which said means responsive to the X and Y signals includes a circuit for comparing signals proportionate to said X and Y signals respectively, and for selecting the coefficients a n , b n employed in said circuits for generating the products a n X and b n Y.
Claim 4
Dependent Claim
53 words
A circuit as defined in claim 1 or claim 2 in which a first set of said coefficients a 1 , b 1 are activated over the range 0≦Z≦w while a second set a 2 , b 2 are enabled in the range w≦Z≦1 where w is a function of X and Y.
Claim 5
Dependent Claim
39 words
A circuit as defined in claim 1 or claim 2 including register stages coupling said absolute value deriving means, said coefficient selecting means and said combining means, and a source of clocking pulses, for pipelining said calculation of r.
Claim 6
Dependent Claim
35 words
A circuit as defined in claim 1 or claim 2 in which said coefficients a 1 . . . a n , b 1 . . . b n have the values of binary fractions.
Claim 7
Dependent Claim
21 words
A circuit as defined in claim 1 or claim 2 in which said means for deriving absolute values comprise logic arrays.
Claim 8
Dependent Claim
31 words
A circuit as defined in claim 1 or claim 2 in which the values of said coefficients are selected to minimize the error between the true and computed value of r.
Claim 9
Dependent Claim
18 words
The circuit as defined in claim 2 in which said product generating circuits are implemented as logic arrays.
Claim 10
Dependent Claim
16 words
A circuit as defined in claim 2 in which said comparing circuit compares Y with 3X/8.
References Cited (Backward Citations)
SU268023A1
Cited
US3829671A
Cited
US3870871A
Cited
US3858036A
Cited
SU642704A1
Cited
SU634271A1
Cited
US4481601A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-07 | 1990-01-06 | 1990-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-07 | 1994-01-06 | 1994-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-07 | 1998-01-06 | 1998-07-08 | $7700.00 | Window Closed / Lapsed |