US3858036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Square root of sum of squares approximator
Assignee: RCA Corp
•
Filing: 1974-02-26
•
Granted: 1974-12-31
•
Expires: 1994-02-26
Abstract
Abstract Circuit for approximating the value of square root (I2 + Q2) using max(I + Q/2, Q + I/2).
Inventors
- 👤 J Lunsford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/552; G06F2207/00; G06F2207/552; G06F2207/5525
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
96 words
The combination comprising: source means for providing signals indicative of two values; comparator means responsive to the source means for providing an output signal indicative of the relative magnitudes of the two values; scaler means responsive to the source means and the output signal from said comparator means for producing quotient signals by dividing the lesser of said two values by two and the greater of said two values by one; and adder means coupled to the scaler means for producing output signals indicative of the sum of the quotieNt signals produced by said scaler means.
Claim 2
Dependent Claim
96 words
The combination comprising: source means for providing signals indicative of two values; comparator means responsive to the source means for providing an output signal indicative of the relative magnitudes of the two values; scaler means responsive to the source means and the output signal from said comparator means for producing quotient signals by dividing the lesser of said two values by two and the greater of said two values by one; and adder means coupled to the scaler means for producing output signals indicative of the sum of the quotieNt signals produced by said scaler means.
Claim 3
Dependent Claim
43 words
The invention claimed in claim 1 wherein said two values are indicated by electrical signals representing binary numbers; and said scaler includes a binary bit shift means for moving each bit signal of the lesser binary number to the next lower significance position.
Claim 4
Dependent Claim
38 words
The invention as claimed in claim 2 further including retiming means for storing the source signals and the output signal from said comparator means and wherein said scaler means is responsive to the values in the retiming means.
Claim 5
Dependent Claim
28 words
The invention as claimed in claim 3 wherein said comparator comprises a subtractor means and the output signal represents a borrow signal from the most significant bit position.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-30 | 1978-07-01 | 1978-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-30 | 1982-07-01 | 1982-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-30 | 1986-07-01 | 1986-12-31 | $7700.00 | Window Closed / Lapsed |