Pulse rate device to compute square root of products

Claim 2

A pulse-rate method for computing the square root of the product of magnitudes which comprises the steps of: continuously converting each of said magnitudes into a series of pulses having a frequency proportional to the magnitude, continuously and separately registering each pulse series in a memory provided therefor, continuously multiplying together the pulse series which have been registered thereby to obtain a resultant signal of the multiplied frequency, dividing said multiplied frequency signal by a fixed number thereby to obtain successive data having a frequency equal to the multiplied frequency divided by said fixed number and which is proportional to the square root of the product of the magnitudes, and applying each of said data to reset one of said memories.

Claim 3

A puLse rate device for computing the square root of the product of magnitudes which comprises: a set of magnitude-to-frequency converters each receiving data corresponding to one of said magnitudes and delivering at its output a corresponding series of pulses at a frequency proportional to the magnitude, a set of memory registers connected respectively to the outputs of said magnitude-to-frequency converters for recording each pulse series, a pulse multiplier connected to the outputs of said memory registers for obtaining the product of the pulse series, and a pulse frequency divider operating with a fixed divisor and connected to receive the output from said pulse multiplier for producing at its output a signal having a frequency proportional to the square root of the product of said magnitudes, the output of said pulse frequency divider being applied to and effecting a reset to zero of one of said memory registers.

Claim 4

A puLse rate device for computing the square root of the product of magnitudes which comprises: a set of magnitude-to-frequency converters each receiving data corresponding to one of said magnitudes and delivering at its output a corresponding series of pulses at a frequency proportional to the magnitude, a set of memory registers connected respectively to the outputs of said magnitude-to-frequency converters for recording each pulse series, a pulse multiplier connected to the outputs of said memory registers for obtaining the product of the pulse series, and a pulse frequency divider operating with a fixed divisor and connected to receive the output from said pulse multiplier for producing at its output a signal having a frequency proportional to the square root of the product of said magnitudes, the output of said pulse frequency divider being applied to and effecting a reset to zero of one of said memory registers.

Claim 5

Device as set forth in claim 2, comprising further a pulse synchronizer circuit connected between the magnitude-to-frequency converters and the memory-registers.

Claim 6

Device as set forth in claim 2, wherein said memory-registers are in the form of binary counters having the same capacity.

Claim 7

Device as set forth in claim 2 wherein each of said memory registers includes a number of stages and wherein said pulse multiplier includes a number of AND circuits equal to the number of stages of said memory registers, each said AND circuit having two inputs and one output, the inputs of said AND circuits being connected respectively to complementary order stages of said memory registers, and the outputs of said AND circuits being connected respectively through differentiation circuits to inputs of an OR circuit having an output connected to a first input of a two-input AND circuit of which the second input thereto is connected to one of said magnitude-to-frequency converters through a NOT circuit.

Claim 8

Device as set forth in claim 2 wherein for computing square root of a product of two magnitudes, the set of magnitude -to-frequency converters comprises two of said converters, the set of memory-registers comprises a first and a second memory-registers and said multiplier is constituted by a third memory-register and by an adder comprising a carrying-over flip-flop and having series inputs connected to outputs of said second and third memory-registers, one output of said adder being connected to input of said second memory register, whereby content of said first memory registers is transferred into said third memory register and added to content of said second memory register upon each pulse received thereby.

Claim 9

Device as set forth in claim 6 and which further comprises a pulse synchronizer circuit connected between said magnitude-to-frequency converters and said memory registers, said pulse synchronizer circuit comprising a pulse counter having its output connected to the input of a decoder thus to provide phase-shifted control pulses.

Claim 10

Device as set forth in claim 7 wherein one of said control pulses is applied to one input of an AND circuit having a second input connected to the output from the said carrying-over flip-flop of said adder, the output of said AND circuit being connected to the input to said pulse frequency divider.

Claim 11

Device as set forth in claim 7 wherein one of said control pulses is applied to said third memory-register to transfer therein the content of the first memory-register.

Claim 12

Device as set forth in claim 7 wherein one of said control pulses is applied to reset the carrying-over flip-flop of said adder.

Claim 13

A pulse rate device for computing the square root of the product of two magnitudes which comprises, a pair of magnitude-to-frequency converters each receiving data corresponding to one of the two magnitudes, first and second memory registers connected respectively to the outputs from said magnitude-to-frequency converters through a pulse synchronizer circuit, and a third memory register connected to an adder through a pulse divider whereby said pulse divider and third memory register form only one register, said adder comprising a carrying-over flip-flop and having series inputs connected to the outputs of said second and third memory registers, one output of said pulse synchronizer being applied to one input of an AND circuit of which a second input is connected to the carrying over flip-flop of said adder, the output of said AND circuit constituting the output of said pulse rate device.

Claim 14

A pulse rate device for computing the square root of the product of two magnitudes which comprises, a pair of magnitude-to-frequency converters each receiving data corresponding to one of the two magnitudes, first and second memory registers connected respectively to the outputs from said magnitude-to-frequency converters through a pulse synchronizer circuit, and a third memory register connected to an adder through a pulse divider whereby said pulse divider and third memory register form only one register, said adder comprising a carrying-over flip-flop and having series inputs connected to the outputs of said second and third memory registers, one output of said pulse synchronizer being applied to one input of an AND circuit of which a second input is connected to the carrying over flip-flop of said adder, the output of said AND circuit constituting the output of said pulse rate device.