US3557348A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital arithmetic system for computation of square roots and squares employing a rate multiplier
Assignee: Westinghouse Electric Corp
•
Filing: 1969-04-09
•
Granted: 1971-01-19
•
Expires: 1989-04-09
Abstract
Abstract Described is a digital system, employing only two binary counters and a rate multiplier, capable of extracting the square root of an unknown variable or raising the unknown variable to the power of two. The system is much simpler and less expensive than prior art systems for achieving the same function.
Inventors
- 👤 Peter F Aemmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:44
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
145 words
In a digital arithmetic system for computing square roots and squares, the combination of a rate multiplier capable of producing a number of output pulses equal to the number of input pulses applied thereto times a multiplying factor, first and second counters, means for applying input pulses to said rate multiplier, means for applying input pulses to said first counter at a frequency rate one-half the frequency rate of pulses applied to said rate multiplier, means for connecting said first counter to said rate multiplier whereby the multiplying factor of said rate multiplier, will be a function of the count stored in said first counter, and means for applying output pulses from said rate multiplier, to the input of said second counter whereby the number of pulses applied to said second counter will be the approximate square of the count stored in said first counter.
Claim 2
Dependent Claim
145 words
In a digital arithmetic system for computing square roots and squares, the combination of a rate multiplier capable of producing a number of output pulses equal to the number of input pulses applied thereto times a multiplying factor, first and second counters, means for applying input pulses to said rate multiplier, means for applying input pulses to said first counter at a frequency rate one-half the frequency rate of pulses applied to said rate multiplier, means for connecting said first counter to said rate multiplier whereby the multiplying factor of said rate multiplier, will be a function of the count stored in said first counter, and means for applying output pulses from said rate multiplier, to the input of said second counter whereby the number of pulses applied to said second counter will be the approximate square of the count stored in said first counter.
Claim 3
Dependent Claim
119 words
The system of claim 1 wherein the said rate multiplier comprises a plurality of flip-flop units connected in cascade, a plurality of AND circuits corresponding in number to the number of flip-flop units, means connecting one output side of each flip-flop in said rate multiplier to an input terminal of an associated one of said AND circuits, said first counter also comprising a plurality of flip-flop units connected in cascade, means connecting one side of each flip-flop of said first counter to an input terminal to an associated one of said AND circuits, and means connecting the outputs of said AND circuits to an OR circuit, the output of the OR circuit being the output of said rate multiplier.
Claim 4
Dependent Claim
44 words
The system of claim 2 wherein said AND circuits have two input terminals only, one of said terminals being connected to an associated flip-flop in said first counter and the other of said terminals being connected to an associated flip-flop in said rate multiplier.
Claim 5
Dependent Claim
81 words
The system of claim 1 wherein pulses are applied to said rate multiplier and said first counter through a gate circuit and wherein said second counter is preset to a number whose square root is to be derived, and means for disabling said gate circuit when said second counter counts down to zero whereby the count of sAid first counter when the gate circuit is disabled will comprise the square root of the number to which said second counter was preset.
Claim 6
Dependent Claim
121 words
The system of claim 1 wherein pulses are applied to said rate multiplier and said first counter through a gate circuit and wherein said first and second counters are initially set to zero and count up, a digital comparator connected to said second counter, a register having a digital output representing a number whose square root is to be determined also connected to said comparator whereby the comparator will produce an output when the count of the second counter matches the digital output of said register, and means for applying said output from the digital comparator to said gate circuit whereby the gate circuit will be disabled when the count of said second counter matches the digital output of said register.
Claim 7
Dependent Claim
17 words
The system of claim 1 wherein said multiplying factor is in the range between zero and 1.999.
Claim 8
Dependent Claim
48 words
The system of claim 4 wherein the output of said second counter is applied to a digital-to-analogue converter, the output of the digital-to-analogue converter being compared with a variable analogue, and means for disabling said gate circuit when the output of said digital-to-analogue converter matches said variable analogue.
Claim 9
Dependent Claim
52 words
The system of claim 4 wherein the count stored in said first counter is applied to a digital-to-analogue converter and the output of said digital-to-analogue converter is compared with a variable analogue signal, and means for disabling said gate circuit when said variable analogue signal matches the output of said digital-to-analogue converter.
Claim 10
Dependent Claim
28 words
The system of claim 4 wherein input pulses are applied through said gate circuit directly to said rate multiplier and through a frequency divider to said first counter.
References Cited (Backward Citations)
US2913179A
Cited
US3049296A
Cited
US3321626A
Cited
US3267267A
Cited
US3225181A
Cited
US3330946A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-18 | 1974-07-20 | 1975-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-18 | 1978-07-20 | 1979-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-18 | 1982-07-20 | 1983-01-19 | $7700.00 | Window Closed / Lapsed |