US3829671A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuit for calculating the square root of the sum of two squares
Assignee: Westinghouse Electric Corp
•
Filing: 1973-04-25
•
Granted: 1974-08-13
•
Expires: 1993-04-25
Abstract
Abstract An arithmetic logic circuit for performing an algorithm which approximates the square root of the sum of two squares. A novel hardware arrangement and method are disclosed which employ EXCLUSIVE OR circuits instead of a conventional 2''s complement arrangement provided by conventional adder-subtractor circuits. The values to be squared are converted to positive value digital signals, compared, and the control signal from a comparison circuit used to command the full value of the larger digital signal and half the value of the smaller digital signal into an adder circuit which receives a correction signal in the event either of the input digital values is negative. The correction signal may be added to the least significant order of the adder output signal or to the next to least significant order depending upon whether the larger or smaller of the digital signals is negative.
Inventors
- 👤 J Gathright
- 👤 R Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/552; G06F2207/00; G06F2207/552; G06F2207/5525
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
238 words
Apparatus for producing an output signal approximating the square root of the sum of the squares of two plural bit binary digital signals where the digital value of each of the two signals may have either a positive or negative sign comprising: a pair of signal channels each containing an initial plural bit binary digital signal and a sign signal; a first circuit means in each signal channel for producing a complement without adding a logical 1 in the least significant order for a digital signal having a negative sign for producing no change in the digital signal having a positive sign; means for generating a control signal determined by the comparative magnitudes of the values of the digital output signals from said first circuit means; a summing circuit; second circuit means including logical circuits responsive to said control signal for applying to the summing circuit a first digital signal having a value of one-half of the value of the output signal from said first circuit means that is the smaller and a second digital signal having the entire value of the output signal from the first circuit means that is the larger; and, a further circuit for applying to the summing circuit a logical 1 in the least significant fractional order in response to either initial digital signal being negative to produce an approximate square root of the sum of the squares of the initial digital signals.
Claim 2
Dependent Claim
238 words
Apparatus for producing an output signal approximating the square root of the sum of the squares of two plural bit binary digital signals where the digital value of each of the two signals may have either a positive or negative sign comprising: a pair of signal channels each containing an initial plural bit binary digital signal and a sign signal; a first circuit means in each signal channel for producing a complement without adding a logical 1 in the least significant order for a digital signal having a negative sign for producing no change in the digital signal having a positive sign; means for generating a control signal determined by the comparative magnitudes of the values of the digital output signals from said first circuit means; a summing circuit; second circuit means including logical circuits responsive to said control signal for applying to the summing circuit a first digital signal having a value of one-half of the value of the output signal from said first circuit means that is the smaller and a second digital signal having the entire value of the output signal from the first circuit means that is the larger; and, a further circuit for applying to the summing circuit a logical 1 in the least significant fractional order in response to either initial digital signal being negative to produce an approximate square root of the sum of the squares of the initial digital signals.
Claim 3
Dependent Claim
57 words
Apparatus as claimed in claim 1 wherein said further circuit comprises a logical OR circuit having two input terminals and having its output terminal connected to the least significant fractional order in said summing circuit, and circuit means for applying the sign signal from each of said signal channels to the input terminals of said OR circuit.
Claim 4
Dependent Claim
87 words
Apparatus as claimed in claim 1 wherein said second circuit means comprises a pair of branch channels connected between the output of said first circuit means and the input to said summing circuit, with one of said branch channels in each pair including a divide-by-two circuit which shifts the plural bit binary digital signal by one order, and gating circuits operative in response to said control signal for selectively applying to said summing circuit the unshifted or the shifted digital signal output from said first circuit means.
Claim 5
Dependent Claim
69 words
Apparatus as claimed in claim 3 wherein said further circuit includes an OR circuit connected to the next to least significant fractional order in said summing circuit, and means responsive to a negative sign signal and said control signal for controlling the OR circuit to produce a logical 1 when the binary digital signal remains unshifted before being applied to the summing circuit and has a negative sign signal.
Claim 6
Dependent Claim
79 words
Apparatus as claimed in claim 1 wherein the first circuit means comprises an EXCLUSIVE OR logical circuit having two input terminals for each bit of the plural bit binary digital signal, means for applying the sign signal of the digital signal to one terminal of all of the EXCLUSIVE OR circuits, and means for applying the binary bit for each separate order of the plural bit binary digital signal to the other terminal of the respective EXCLUSIVE OR circuit.
Claim 7
Dependent Claim
56 words
Apparatus as claimed in claim 5 wherein said further circuit comprises a logical OR circuit having two input terminals and having its output terminal connected to the least significant fractional order in said summing circuit, and circuit means for applying the sign signal from each of said signal channels to input terminals of said OR circuit.
Claim 8
Dependent Claim
73 words
Apparatus as claimed in claim 5 wherein said second circuit means comprises a pair of branch channels connected between the output of said branch channels in each pair including a divide-by-two circuit which shifts the plural bit binary digital signal by one order, and gating circuits operative in response to said control signal for selectively applying to said summing circuit the unshifted or the shifted digital signal output from said first circuit means.
Claim 9
Dependent Claim
134 words
Apparatus as claimed in claim 7 wherein said further circuit comprises first and second logical OR circuits with the output terminal of the first OR circuit connected to the least significant fractional order in said summing circuit and the output terminal of the second OR circuit connected to the next to least significant fractional order in said summing circuit, and means responsive to a negative sign signal and said control signal for controlling the first OR circuit to produce a logical 1 when the binary digital signal that has been shifted before being applied to the summing circuit has a negative sign and for controlling the second OR circuit to produce a logical 1 when the binary digital signal remains unshifted before being applied to the summing circuit and has a negative sign signal.
Claim 10
Independent Claim
197 words
A method for approximating the square root of the sum of two squares where the digital value of each may have either a positive or negative sign by: providing a pair of initial plural bit binary digital signals each having a sign signal indicating a positive or negative value; complementing each digital signal having a negative value without adding a logical 1 in the least significant order to convert such signals to positive value digital signals; determining which of the pair of positive value digital signals has the largest value; summing one half of the value of the smaller digital signal with the entire value of the larger digital signal to produce an approximate square root digital signal of the sum of the squares of the pair of initial digital signals; and, correcting the square root digital signal for any negative value of an initial digital signal by monitoring the sign signal of each of the initial digital signals, producing a logical 1 in response to either sign signal being negative and adding the logical 1 to the least significant order of the approximate square root digital signal to produce a corrected approximate square root digital signal.
Claim 11
Independent Claim
197 words
A method for approximating the square root of the sum of two squares where the digital value of each may have either a positive or negative sign by: providing a pair of initial plural bit binary digital signals each having a sign signal indicating a positive or negative value; complementing each digital signal having a negative value without adding a logical 1 in the least significant order to convert such signals to positive value digital signals; determining which of the pair of positive value digital signals has the largest value; summing one half of the value of the smaller digital signal with the entire value of the larger digital signal to produce an approximate square root digital signal of the sum of the squares of the pair of initial digital signals; and, correcting the square root digital signal for any negative value of an initial digital signal by monitoring the sign signal of each of the initial digital signals, producing a logical 1 in response to either sign signal being negative and adding the logical 1 to the least significant order of the approximate square root digital signal to produce a corrected approximate square root digital signal.
Claim 12
Dependent Claim
62 words
The method as claimed in claim 9 wherein the initial plural bit binary digital signals are applied to a bank of EXCLUSIVE OR gates arranged to produce the 2''s complement of each digital signal having a negative value without adding a logical 1 in the least significant order and for passing each digital signal having a positive value without change of value.
Claim 13
Dependent Claim
70 words
The method as claimed in claim 10 wherein the square root digital signal is corrected by adding a logical 1 to the least signIficant order of the approximate square root digital signal when the smaller digital signal has a negative sign signal and adding a logical 1 to the next to least significant order of the square root digital signal when the larger digital signal has a negative sign bit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-12 | 1978-02-11 | 1978-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-12 | 1982-02-11 | 1982-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-12 | 1986-02-11 | 1986-08-13 | $7700.00 | Window Closed / Lapsed |