Floating-gate memory cell

Claim 1

A floating gate memory cell in which writing and erasing are effected by the injection of hot charge carriers comprising: a substrate having a first selected doping; a memory transistor coupled to a selection transistor and carried by said substrate, said transistors formed as insulated gate field effect transistors; a reading line formed in said substrate adjacent said selection transistor; a programming line formed in said substrate adjacent said memory transistor; said transistors each including a channel region wherein said channel region of said memory transistor is directly coupled to said channel region of said selection transistor with said channel regions located between said lines; a common-gate oxide area of a thickness formed on said substrate overlying said channels, as well as a region of said reading line and extending a selected distance across a region of said programming line and over said substrate forming an extension region; a programming region of a second selected doping formed in said substrate at a surface thereof beneath said extension region of said oxide with said programming region having the same type of doping as said substrate; a floating gate formed over a region of said oxide area, said gate overlying said channel of said memory transistor, said programming line and a selected part of said programming region, exclusive of that part of said oxide that overlies said channel of said selection transistor; and a control gate overlying said floating gate, insulated therefrom, and said oxide; said control gate, said reading line and said programming line all forming electrodes of the memory cell.