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JPS54156484A Expired / Lapsed JP ⏱️ 0.0 years remaining

Non-volatile semiconductor memory device

Assignee: NEC Corp
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Filing: 1978-05-30
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Granted: —
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Expires: 1998-05-30
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Abstract

Abstract PURPOSE:To increase gm, by placing the high concentration region of the same type as the substrate to a part of the source or drain layer with self-alignment, covering the floating gate electrode locally with this region, and determining a part of the shape with self-alignment to the control gate electrode. CONSTITUTION:On the gate oxide film 4 on the P<-> type Si substrate 1, the control electrode 7 of phosphorus added polycrystal Si is placed via the floating gate electrode 5 of phosphorus added polycrystal Si and second gate oxide film 6. The electrode 5 is determined for the shape with self-alignment partly to the electrode 7, and the ends are in agreement. The P layer 8 is provided with self-alignment by B ion injection, by taking the electrode as a mask, phosphorus is added with self- alignment to form the N<+> layers 9 and 10. Next, the electrodes 13 and 14 are attached with selective open window. Since the hot carrier injection is located near the drain, it is not necessary to coat the overall channel by the electrode 5, the area of the electrode 5 is taken small, the threshold voltage is changed greater, and further, the channel part opposing to the electrode 6 directly obtains greater conductiviry with the control voltage than others, to form the memrory device excellent in performance.

Inventors

  • 👤 Masanori Kikuchi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 02:22
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686

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