Constant current source for integrated circuits

Claim 2

An integrated circuit comprising: a current source comprising a bias-providing transistor for supplying a stabilized current; a control transistor which is matched to the current source transistor, and which has its current-determining voltage in parallel with the current-determining voltage of the current source transistor; means for intermittently equalizing the voltages of the control and current source transistors; and means for applying a linear ramp voltage to develop a substantially constant amount of current in the control transistor.

Claim 3

The integrated circuit of claim 1 in which the linear ramp voltage applying means includes a capacitor, one side of which is connected to both the voltage and the current branches of the control transistor, and the other side of which is connected to a waveform generator.

Claim 4

The integrated circuit of claim 1 which also comprises: a capacitor connected in parallel with the voltage across the current-bias-providing transistor, between two voltage reference terminals; a normally open switch between one of those voltage reference terminals and a voltage reference terminal of the control transistor; and means for periodically closing the switch to maintain substantially equalized voltage across the control and current-bias-providing transistors.

Claim 5

The integrated circuit of claim 3 wherein the switch is an insulated gate field effect transistor, whose source-to-drain channel is connected between the voltage reference terminals, and whose gate is connected to a wave-form generator.

Claim 6

In a circuit having integrated circuitry on a substrate which includes circuitry requiring a substantially constant current bias source, and means external to the integrated circuitry for providing a voltage waveform source, an integrated circuit current source comprising: first and second voltage reference terminals; a MOSFET current-source transistor whose source-to-drain current provides the substantially constant bias current, and whose gate-to-source voltage is connected between the first and second voltage reference terminals; a diode-connected MOSFET control transistor whose gate-to-source voltage is connected between the first reference terminal and a third reference terminal provided by its interconnected gate and drain; a first capacitor connected between the first and second reference terminals for the purpose of stabilizing the gate-to-source voltage of the current-source transistor; a normally open switch connected between the second and third reference terminals, and periodically closed to maintain substantial equalization of the voltages on the control and current-source transistors; a second capacitor having its first side connected to the third voltage reference terminal and to the source-to-drain current of the control transistor, and having its second side connected to the external waveform source; and means for applying a linear ramp voltage from the waveform source to the second side of the second capacitor in such a way as to enable the control transistor and cause in it a constant source-to-drain current flow which is mirrored in the current-source transistor; the geometries of the control transistor and current-source transistor being such that their respective amounts of current have the same ratio to one another whenever the same voltage is applied to both transistors.

Claim 7

In a circuit having integrated circuitry on a substrate which includes circuitry requiring a substantially constant current bias source, and means external to the integrated circuitry for providing a voltage waveform source, an integrated circuit current source comprising: first and second voltage reference terminals; a MOSFET current-source transistor whose source-to-drain current provides the substantially constant bias current, and whose gate-to-source voltage is connected between the first and second voltage reference terminals; a diode-connected MOSFET control transistor whose gate-to-source voltage is connected between the first reference terminal and a third reference terminal provided by its interconnected gate and drain; a first capacitor connected between the first and second reference terminals for the purpose of stabilizing the gate-to-source voltage of the current-source transistor; a normally open switch connected between the second and third reference terminals, and periodically closed to maintain substantial equalization of the voltages on the control and current-source transistors; a second capacitor having its first side connected to the third voltage reference terminal and to the source-to-drain current of the control transistor, and having its second side connected to the external waveform source; and means for applying a linear ramp voltage from the waveform source to the second side of the second capacitor in such a way as to enable the control transistor and cause in it a constant source-to-drain current flow which is mirrored in the current-source transistor; the geometries of the control transistor and current-source transistor being such that their respective amounts of current have the same ratio to one another whenever the same voltage is applied to both transistors.

Claim 8

The circuit of claim 5 in which both the current-source MOSFET transistor and the control MOSFET transistor are P-channel devices.

Claim 9

The circuit of claim 5 in which both the current-source MOSFET transistor and the control MOSFET transistor are N-channel devices.

Claim 10

The circuit of claim 5 in which the current return flow when the control transistor is disabled is transmitted via a forward-biased diode effect between the transistor and the substrate of the integrated circuit.

Claim 11

The circuit of claim 5 in which the switch is a MOSFET transistor having its source-to-drain current connected between the second and third voltage reference terminals, and its gate connected to the external waveform source.

Claim 12

The circuit of claim 9 in which the external waveform source causes the switch MOSFET to be enabled only during a short pulse occurring near the end of the linear ramp voltage waveform which produces constant current flow in the control transistor.

Claim 13

The circuit of claim 5 which includes a plurality of parallel current-source transistors, each having the same relationship with the control transistor.

Claim 14

The circuit of claim 5 which also comprises: an additional transistor which provides a current return path during the periods when the control transistor is disabled.