Non-overlapping clock CMOS circuit with two threshold voltages

Claim 1

A CMOS integrated circuit comprising: clock means for generating at least one clock signal; clock distribution means for distributing said at least one clock signal to selected points within said integrated circuit; a high voltage distribution network; a ground distribution network; at least two controllable logic circuits, each having an input terminal, an output terminal and a control terminal, for performing logical operations under control of a clock signal at said control terminal, on an input signal on said input terminal; characterized in that: said clock means generates two non-overlapping clock signals; said distribution means comprises two electrically isolated distribution networks for distributing said two non-overlapping clock signals; and all of said at least two controllable logic circuits comprise at least one transmission gate and at least one logic unit, said at least one transmission gate and logic unit sharing an intermediate node that couples the output of said transmission gate to the input of said logic unit; each controllable logic circuit comprises a pull-up section connected between said high voltage distribution network and said output terminal of said logic circuit and a pull-down section connected between said output terminal of said logic circuit and said ground distribution network; in which controllable logic circuits, all of said transmission gates comprise at least one N-channel pass transistor connected between said input terminal and said intermediate node and having a gate controlled by one of said non-overlapping clock signals, said N-channel pass transistors all having a standard threshold voltage; and in which controllable logic circuits all of said pull-down sections comprise at least one N-channel transistor having said standard threshold voltage and being connected in a path between said output terminal and ground and having a gate connected by signal transfer means to said intermediate node; and in which controllable logic circuits all of said pull-up sections comprise at least one P-channel transistor having a non-standard P-channel negative threshold of absolute value greater than 1.5 volts connected in a path between said high voltage distribution network and said output terminal and having a gate connected by signal transfer means to said intermediate node; whereby said controllable logic circuits in said CMOS integrated circuit may be constructed with only two different threshold voltages: a standard N-channel threshold voltage; and a non-standard P-channel threshold voltage.